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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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-- Entity: GpibSynchronizer
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-- Entity: GpibSynchronizer
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-- Date:2012-02-06
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-- Date:2012-02-06
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-- Author: andrzej
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity GpibSynchronizer is
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entity GpibSynchronizer is
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port (
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port (
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-- clk
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-- clk
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clk : std_logic;
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clk : std_logic;
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-- DIO
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-- DIO
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DI : in std_logic_vector (7 downto 0);
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DI : in std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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-- attention
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-- attention
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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-- data valid
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-- data valid
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DAV_in : in std_logic;
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DAV_in : in std_logic;
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DAV_out : out std_logic;
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DAV_out : out std_logic;
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-- not ready for data
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-- not ready for data
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NRFD_in : in std_logic;
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NRFD_in : in std_logic;
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NRFD_out : out std_logic;
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NRFD_out : out std_logic;
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-- no data accepted
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-- no data accepted
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NDAC_in : in std_logic;
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NDAC_in : in std_logic;
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NDAC_out : out std_logic;
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NDAC_out : out std_logic;
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-- end or identify
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-- end or identify
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EOI_in : in std_logic;
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EOI_in : in std_logic;
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EOI_out : out std_logic;
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EOI_out : out std_logic;
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-- service request
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-- service request
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SRQ_in : in std_logic;
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SRQ_in : in std_logic;
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SRQ_out : out std_logic;
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SRQ_out : out std_logic;
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-- interface clear
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-- interface clear
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IFC_in : in std_logic;
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IFC_in : in std_logic;
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IFC_out : out std_logic;
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IFC_out : out std_logic;
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-- remote enable
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-- remote enable
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REN_in : in std_logic;
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REN_in : in std_logic;
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REN_out : out std_logic
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REN_out : out std_logic
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);
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);
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end GpibSynchronizer;
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end GpibSynchronizer;
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architecture arch of GpibSynchronizer is
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architecture arch of GpibSynchronizer is
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begin
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begin
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process(clk) begin
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process(clk) begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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DO <= DI;
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DO <= DI;
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ATN_out <= ATN_in;
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ATN_out <= ATN_in;
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DAV_out <= DAV_in;
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DAV_out <= DAV_in;
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NRFD_out <= NRFD_in;
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NRFD_out <= NRFD_in;
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NDAC_out <= NDAC_in;
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NDAC_out <= NDAC_in;
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EOI_out <= EOI_in;
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EOI_out <= EOI_in;
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SRQ_out <= SRQ_in;
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SRQ_out <= SRQ_in;
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IFC_out <= IFC_in;
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IFC_out <= IFC_in;
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REN_out <= REN_in;
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REN_out <= REN_in;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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