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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: gpibWriter
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-- Entity: gpibWriter
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-- Date: 2011-11-01
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-- Date: 2011-11-01
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.utilPkg.all;
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use work.utilPkg.all;
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entity gpibWriter is
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entity gpibWriter is
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port (
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port (
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-- clock
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-- clock
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clk : in std_logic;
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clk : in std_logic;
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-- reset
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-- reset
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reset : std_logic;
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reset : std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------ GPIB interface --------------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- output data
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-- output data
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data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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-- wait for new cycle
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-- wait for new cycle
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wnc : in std_logic;
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wnc : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-- new byte available
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-- new byte available
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nba : out std_logic;
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nba : out std_logic;
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-- end of string
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-- end of string
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endOf : out std_logic;
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endOf : out std_logic;
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-- talker active
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-- talker active
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tac : in std_logic;
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tac : in std_logic;
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-- controller write command
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-- controller write command
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cwrc : in std_logic;
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cwrc : in std_logic;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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------ external interface ----------------------------------------------
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------ external interface ----------------------------------------------
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- TE is extended
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-- TE is extended
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isTE : in std_logic;
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isTE : in std_logic;
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-- current secondary address
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-- current secondary address
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secAddr : in std_logic_vector (4 downto 0);
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secAddr : in std_logic_vector (4 downto 0);
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-- secondary address of data
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-- secondary address of data
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dataSecAddr : in std_logic_vector (4 downto 0);
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dataSecAddr : in std_logic_vector (4 downto 0);
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-- buffer consumed
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-- buffer consumed
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buf_interrupt : out std_logic;
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buf_interrupt : out std_logic;
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-- indicates end of stream
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-- indicates end of stream
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end_of_stream : in std_logic;
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end_of_stream : in std_logic;
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-- resets writer
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-- resets writer
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reset_writer : in std_logic;
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reset_writer : in std_logic;
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-- enables writer
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-- enables writer
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writer_enable : in std_logic;
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writer_enable : in std_logic;
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---------------- fifo ---------------------------
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---------------- fifo ---------------------------
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availableFifoBytesCount : in std_logic_vector(10 downto 0);
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availableFifoBytesCount : in std_logic_vector(10 downto 0);
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-- fifo read strobe
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-- fifo read strobe
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fifo_read_strobe : out std_logic;
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fifo_read_strobe : out std_logic;
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-- indicates fifo ready to read
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-- indicates fifo ready to read
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fifo_ready_to_read : in std_logic;
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fifo_ready_to_read : in std_logic;
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-- input data
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-- input data
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fifo_data_in : in std_logic_vector (7 downto 0)
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fifo_data_in : in std_logic_vector (7 downto 0)
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);
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);
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end gpibWriter;
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end gpibWriter;
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architecture arch of gpibWriter is
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architecture arch of gpibWriter is
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-- writer states
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-- writer states
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type WRITER_STATE is (
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type WRITER_STATE is (
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ST_IDLE,
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ST_IDLE,
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ST_WAIT_WNC_1,
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ST_WAIT_WNC_1,
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ST_WAIT_WNC_0
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ST_WAIT_WNC_0
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);
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);
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signal current_state : WRITER_STATE;
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signal current_state : WRITER_STATE;
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-- triggered by spa
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-- triggered by spa
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signal tr_by_spa : std_logic;
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signal tr_by_spa : std_logic;
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signal readyToSend : boolean;
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signal readyToSend : boolean;
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signal at_least_one_byte_in_fifo : boolean;
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signal at_least_one_byte_in_fifo : boolean;
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begin
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begin
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buf_interrupt <= to_stdl(not at_least_one_byte_in_fifo);
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buf_interrupt <= to_stdl(not at_least_one_byte_in_fifo);
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data_out <= fifo_data_in;
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data_out <= fifo_data_in;
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at_least_one_byte_in_fifo <= availableFifoBytesCount /= "000000000000";
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at_least_one_byte_in_fifo <= availableFifoBytesCount /= "000000000000";
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readyToSend <=
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readyToSend <=
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(
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(
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writer_enable = '1'
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writer_enable = '1'
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and
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and
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at_least_one_byte_in_fifo
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at_least_one_byte_in_fifo
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and
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and
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(
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(
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(
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(
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tac='1'
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tac='1'
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and
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and
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(
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(
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(isTE='1' and dataSecAddr=secAddr)
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(isTE='1' and dataSecAddr=secAddr)
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or
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or
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isTE='0'
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isTE='0'
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)
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)
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)
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)
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or
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or
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cwrc='1'
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cwrc='1'
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)
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)
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and
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and
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fifo_ready_to_read='1'
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fifo_ready_to_read='1'
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)
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)
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or
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or
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spa='1';
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spa='1';
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process (clk, reset, reset_writer) begin
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process (clk, reset, reset_writer) begin
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if reset = '1' or reset_writer = '1' then
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if reset = '1' or reset_writer = '1' then
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nba <= '0';
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nba <= '0';
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endOf <= '0';
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endOf <= '0';
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fifo_read_strobe <= '0';
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fifo_read_strobe <= '0';
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tr_by_spa <= '0';
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tr_by_spa <= '0';
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case current_state is
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case current_state is
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when ST_IDLE =>
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when ST_IDLE =>
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if readyToSend then
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if readyToSend then
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nba <= '1';
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nba <= '1';
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tr_by_spa <= spa;
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tr_by_spa <= spa;
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if availableFifoBytesCount="000000000001" and
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if availableFifoBytesCount="000000000001" and
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end_of_stream='1' and spa='0' and tac='1' and
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end_of_stream='1' and spa='0' and tac='1' and
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cwrc='0' then
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cwrc='0' then
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endOf <= '1';
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endOf <= '1';
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end if;
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end if;
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current_state <= ST_WAIT_WNC_1;
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current_state <= ST_WAIT_WNC_1;
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end if;
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end if;
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when ST_WAIT_WNC_1 =>
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when ST_WAIT_WNC_1 =>
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if wnc='1' then
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if wnc='1' then
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nba <= '0';
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nba <= '0';
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if tr_by_spa='0' then
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if tr_by_spa='0' then
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endOf <= '0';
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endOf <= '0';
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fifo_read_strobe <= '1';
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fifo_read_strobe <= '1';
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end if;
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end if;
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current_state <= ST_WAIT_WNC_0;
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current_state <= ST_WAIT_WNC_0;
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end if;
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end if;
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when ST_WAIT_WNC_0 =>
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when ST_WAIT_WNC_0 =>
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if wnc='0' then
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if wnc='0' then
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if tr_by_spa='0' then
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if tr_by_spa='0' then
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fifo_read_strobe <= '0';
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fifo_read_strobe <= '0';
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end if;
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end if;
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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current_state <= ST_IDLE;
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current_state <= ST_IDLE;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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