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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: InterruptGenerator
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-- Entity: InterruptGenerator
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-- Date:2011-11-25
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-- Date:2011-11-25
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.helperComponents.all;
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use work.helperComponents.all;
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entity InterruptGenerator is
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entity InterruptGenerator is
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port (
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port (
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reset : std_logic;
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reset : std_logic;
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clk : in std_logic;
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clk : in std_logic;
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interrupt : out std_logic;
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interrupt : out std_logic;
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-------------------- gpib device ---------------------
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-------------------- gpib device ---------------------
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-- device is local controlled
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-- device is local controlled
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isLocal : in std_logic;
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isLocal : in std_logic;
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-- input buffer ready
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-- input buffer ready
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in_buf_ready : in std_logic;
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in_buf_ready : in std_logic;
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-- output buffer ready
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-- output buffer ready
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out_buf_ready : in std_logic;
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out_buf_ready : in std_logic;
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-- clear device (DC)
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-- clear device (DC)
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clr : in std_logic;
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clr : in std_logic;
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-- trigger device (DT)
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-- trigger device (DT)
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trg : in std_logic;
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trg : in std_logic;
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-- addressed to talk(L or LE)
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-- addressed to talk(L or LE)
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att : in std_logic;
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att : in std_logic;
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-- addressed to listen (T or TE)
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-- addressed to listen (T or TE)
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atl : in std_logic;
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atl : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-------------------- gpib controller ---------------------
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-------------------- gpib controller ---------------------
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-- controller write commands
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-- controller write commands
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cwrc : in std_logic;
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cwrc : in std_logic;
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-- controller write data
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-- controller write data
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cwrd : in std_logic;
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cwrd : in std_logic;
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-- service requested
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-- service requested
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srq : in std_logic;
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srq : in std_logic;
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-- parallel poll ready
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-- parallel poll ready
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ppr : in std_logic;
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ppr : in std_logic;
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-- stb received
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-- stb received
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stb_received : in std_logic;
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stb_received : in std_logic;
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REN : in std_logic;
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REN : in std_logic;
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ATN : in std_logic;
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ATN : in std_logic;
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IFC : in std_logic
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IFC : in std_logic
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);
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);
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end InterruptGenerator;
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end InterruptGenerator;
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architecture arch of InterruptGenerator is
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architecture arch of InterruptGenerator is
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constant PULSE_WIDTH : integer := 10;
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constant PULSE_WIDTH : integer := 10;
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signal p0, p1, p2, p3, p4, p5, p6, p7 : std_logic;
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signal p0, p1, p2, p3, p4, p5, p6, p7 : std_logic;
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begin
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begin
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interrupt <= p0 or p1 or p2 or p3 or p4 or p5 or p6 or p7;
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interrupt <= p0 or p1 or p2 or p3 or p4 or p5 or p6 or p7;
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ed0: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed0: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => in_buf_ready, pulse => p0
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reset => reset, clk => clk, in_data => in_buf_ready, pulse => p0
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);
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);
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ed1: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed1: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => out_buf_ready, pulse => p1
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reset => reset, clk => clk, in_data => out_buf_ready, pulse => p1
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);
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);
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ed2: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed2: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => clr, pulse => p2
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reset => reset, clk => clk, in_data => clr, pulse => p2
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);
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);
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ed3: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed3: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => trg, pulse => p3
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reset => reset, clk => clk, in_data => trg, pulse => p3
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);
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);
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ed4: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed4: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => srq, pulse => p4
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reset => reset, clk => clk, in_data => srq, pulse => p4
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);
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);
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ed5: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed5: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => ppr, pulse => p5
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reset => reset, clk => clk, in_data => ppr, pulse => p5
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);
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);
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ed6: EdgeDetector generic map (RISING => '1', FALLING => '0',
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ed6: EdgeDetector generic map (RISING => '1', FALLING => '0',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => stb_received, pulse => p6
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reset => reset, clk => clk, in_data => stb_received, pulse => p6
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);
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);
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ed7: EdgeDetector generic map (RISING => '1', FALLING => '1',
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ed7: EdgeDetector generic map (RISING => '1', FALLING => '1',
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PULSE_WIDTH => PULSE_WIDTH) port map (
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PULSE_WIDTH => PULSE_WIDTH) port map (
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reset => reset, clk => clk, in_data => isLocal, pulse => p7
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reset => reset, clk => clk, in_data => isLocal, pulse => p7
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);
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);
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end arch;
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end arch;
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