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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: SettingsReg0
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-- Entity: SettingsReg0
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-- Date:2011-11-09
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-- Date:2011-11-09
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity SettingsReg0 is
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entity SettingsReg0 is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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strobe : in std_logic;
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strobe : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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------------- gpib -----------------------------
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------------- gpib -----------------------------
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isLE_TE : out std_logic;
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isLE_TE : out std_logic;
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lpeUsed : out std_logic;
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lpeUsed : out std_logic;
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fixedPpLine : out std_logic_vector (2 downto 0);
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fixedPpLine : out std_logic_vector (2 downto 0);
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eosUsed : out std_logic;
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eosUsed : out std_logic;
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eosMark : out std_logic_vector (7 downto 0);
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eosMark : out std_logic_vector (7 downto 0);
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lon : out std_logic;
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lon : out std_logic;
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ton : out std_logic
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ton : out std_logic
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);
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);
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end SettingsReg0;
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end SettingsReg0;
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architecture arch of SettingsReg0 is
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architecture arch of SettingsReg0 is
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signal inner_buf : std_logic_vector (15 downto 0);
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signal inner_buf : std_logic_vector (15 downto 0);
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begin
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begin
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data_out <= inner_buf;
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data_out <= inner_buf;
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isLE_TE <= inner_buf(0);
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isLE_TE <= inner_buf(0);
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lpeUsed <= inner_buf(1);
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lpeUsed <= inner_buf(1);
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fixedPpLine <= inner_buf(4 downto 2);
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fixedPpLine <= inner_buf(4 downto 2);
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eosUsed <= inner_buf(5);
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eosUsed <= inner_buf(5);
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eosMark <= inner_buf(13 downto 6);
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eosMark <= inner_buf(13 downto 6);
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lon <= inner_buf(14);
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lon <= inner_buf(14);
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ton <= inner_buf(15);
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ton <= inner_buf(15);
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process (reset, strobe) begin
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process (reset, strobe) begin
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if reset = '1' then
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if reset = '1' then
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inner_buf <= "0000000000000000";
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inner_buf <= "0000000000000000";
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elsif rising_edge(strobe) then
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elsif rising_edge(strobe) then
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inner_buf <= data_in;
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inner_buf <= data_in;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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