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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: gpibControlReg
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-- Entity: gpibControlReg
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-- Date:2011-11-12
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-- Date:2011-11-12
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity gpibControlReg is
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entity gpibControlReg is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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strobe : in std_logic;
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strobe : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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------------------ gpib ------------------------
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------------------ gpib ------------------------
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ltn : out std_logic; -- listen (L, LE)
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ltn : out std_logic; -- listen (L, LE)
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lun : out std_logic; -- local unlisten (L, LE)
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lun : out std_logic; -- local unlisten (L, LE)
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rtl : out std_logic; -- return to local (RL)
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rtl : out std_logic; -- return to local (RL)
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rsv : out std_logic; -- request service (SR)
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rsv : out std_logic; -- request service (SR)
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ist : out std_logic; -- individual status (PP)
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ist : out std_logic; -- individual status (PP)
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lpe : out std_logic; -- local poll enable (PP)
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lpe : out std_logic; -- local poll enable (PP)
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------------------------------------------------
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------------------------------------------------
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rsc : out std_logic; -- request system control (C)
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rsc : out std_logic; -- request system control (C)
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sic : out std_logic; -- send interface clear (C)
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sic : out std_logic; -- send interface clear (C)
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sre : out std_logic; -- send remote enable (C)
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sre : out std_logic; -- send remote enable (C)
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gts : out std_logic; -- go to standby (C)
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gts : out std_logic; -- go to standby (C)
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tcs : out std_logic; -- take control synchronously (C, AH)
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tcs : out std_logic; -- take control synchronously (C, AH)
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tca : out std_logic; -- take control asynchronously (C)
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tca : out std_logic; -- take control asynchronously (C)
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rpp : out std_logic; -- request parallel poll (C)
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rpp : out std_logic; -- request parallel poll (C)
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rec_stb : out std_logic -- receives status byte (C)
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rec_stb : out std_logic -- receives status byte (C)
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);
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);
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end gpibControlReg;
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end gpibControlReg;
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architecture arch of gpibControlReg is
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architecture arch of gpibControlReg is
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signal inner_buf : std_logic_vector (15 downto 0);
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signal inner_buf : std_logic_vector (15 downto 0);
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begin
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begin
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ltn <= inner_buf(0);
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ltn <= inner_buf(0);
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lun <= inner_buf(1);
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lun <= inner_buf(1);
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rtl <= inner_buf(2);
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rtl <= inner_buf(2);
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rsv <= inner_buf(3);
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rsv <= inner_buf(3);
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ist <= inner_buf(4);
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ist <= inner_buf(4);
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lpe <= inner_buf(5);
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lpe <= inner_buf(5);
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------------------------------------------------
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------------------------------------------------
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rsc <= inner_buf(6);
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rsc <= inner_buf(6);
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sic <= inner_buf(7);
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sic <= inner_buf(7);
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sre <= inner_buf(8);
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sre <= inner_buf(8);
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gts <= inner_buf(9);
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gts <= inner_buf(9);
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tcs <= inner_buf(10);
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tcs <= inner_buf(10);
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tca <= inner_buf(11);
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tca <= inner_buf(11);
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rpp <= inner_buf(12);
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rpp <= inner_buf(12);
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rec_stb <= inner_buf(13);
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rec_stb <= inner_buf(13);
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data_out <= inner_buf;
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data_out <= inner_buf;
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process (reset, strobe) begin
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process (reset, strobe) begin
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if reset = '1' then
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if reset = '1' then
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inner_buf <= "0000000000000000";
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inner_buf <= "0000000000000000";
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elsif rising_edge(strobe) then
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elsif rising_edge(strobe) then
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inner_buf <= data_in;
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inner_buf <= data_in;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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