/* Constraints */
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/* Constraints */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */
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DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */
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DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */
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DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */
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|
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/* Clocks constraints */
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/* Clocks constraints */
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create_clock CLK -period CLK_PERIOD
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create_clock CLK -period CLK_PERIOD
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create_clock ECLK -period CLK_PERIOD
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create_clock ECLK -period CLK_PERIOD
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_dont_touch_network all_clocks()
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set_dont_touch_network all_clocks()
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/* Reset constraints */
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/* Reset constraints */
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set_driving_cell -none RST
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set_driving_cell -none RST
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set_drive 0 RST
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set_drive 0 RST
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set_dont_touch_network RST
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set_dont_touch_network RST
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|
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/* All inputs except reset and clock */
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/* All inputs except reset and clock */
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all_inputs_wo_rst_clk = all_inputs() - CLK - RST
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all_inputs_wo_rst_clk = all_inputs() - CLK - RST
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|
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/* Set output delays and load for output signals
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/* Set output delays and load for output signals
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*
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*
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* All outputs are assumed to go directly into
|
* All outputs are assumed to go directly into
|
* external flip-flops for the purpose of this
|
* external flip-flops for the purpose of this
|
* synthesis
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* synthesis
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*/
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*/
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set_output_delay DFFHQX2_SETUP -clock CLK all_outputs()
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set_output_delay DFFHQX2_SETUP -clock CLK all_outputs()
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set_load load_of(typical/DFFHQX2/D) * 1 all_outputs()
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set_load load_of(typical/DFFHQX2/D) * 1 all_outputs()
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|
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/* Input delay and driving cell of all inputs
|
/* Input delay and driving cell of all inputs
|
*
|
*
|
* All these signals are assumed to come directly from
|
* All these signals are assumed to come directly from
|
* flip-flops for the purpose of this synthesis
|
* flip-flops for the purpose of this synthesis
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*
|
*
|
*/
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*/
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set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk
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set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk
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set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk
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set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk
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|
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/* Set design fanout */
|
/* Set design fanout */
|
/*
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/*
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set_max_fanout 10 TOPLEVEL
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set_max_fanout 10 TOPLEVEL
|
*/
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*/
|
|
|
/* Set area constraint */
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/* Set area constraint */
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set_max_area MAX_AREA
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set_max_area MAX_AREA
|
|
|
/* Optimize all near-critical paths to give extra slack for layout */
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/* Optimize all near-critical paths to give extra slack for layout */
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c_range = CLK_PERIOD * 0.05
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c_range = CLK_PERIOD * 0.05
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group_path -critical_range c_range -name CLK -to CLK
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group_path -critical_range c_range -name CLK -to CLK
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|
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/* Operating conditions */
|
/* Operating conditions */
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set_operating_conditions typical
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set_operating_conditions typical
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