| Line 31... |
Line 31... |
entity high_load is
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entity high_load is
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generic (
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generic (
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NUM_IN : positive := 3*14; -- Input pins
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NUM_IN : positive := 3*14; -- Input pins
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NUM_OUT : positive := 1; -- Output pins
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NUM_OUT : positive := 1; -- Output pins
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NUM_LC : positive := 16; -- Number of LC cores
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NUM_LC : positive := 16; -- Number of LC cores
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LC_RECURSION : positive := 1; -- 1 = no recursion
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NUM_DSP : positive := 9; -- Number of DSP cores
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NUM_DSP : positive := 9; -- Number of DSP cores
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RAM_DEPTH_LOG2 : integer range 4 to 30 := 10 -- RAM depth
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RAM_DEPTH_LOG2 : integer range 4 to 30 := 10 -- RAM depth
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);
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);
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port
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port
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(
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(
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| Line 60... |
Line 61... |
-- );
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-- );
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--end component;
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--end component;
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|
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component lc_use is
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component lc_use is
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generic (
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generic (
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RECURSION_IDX : positive := 1; -- 1 = stop recursion
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DATA_WIDTH : positive := 128;
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DATA_WIDTH : positive := 128;
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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NUM_ROWS: positive := 6; -- Input pins
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NUM_ROWS: positive := 6; -- Input pins
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ADD_PIPL_FF : boolean := false
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ADD_PIPL_FF : boolean := false
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);
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);
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-- key => to_stdlogicvector(key rol i),
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-- key => to_stdlogicvector(key rol i),
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-- dataout=> aes_out(128*i+127 downto 128*i)
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-- dataout=> aes_out(128*i+127 downto 128*i)
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-- );
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-- );
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lc_i: lc_use
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lc_i: lc_use
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generic map (
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generic map (
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RECURSION_IDX => LC_RECURSION,
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DATA_WIDTH => 128,
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DATA_WIDTH => 128,
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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NUM_ROWS => 6, -- Input pins
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NUM_ROWS => 6, -- Input pins
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ADD_PIPL_FF => true
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ADD_PIPL_FF => true
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)
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)
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