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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.2 2001-11-05 11:59:25 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.3 2002-06-15 07:37:03 rherveille Exp $
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//
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//
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// $Date: 2001-11-05 11:59:25 $
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// $Date: 2002-06-15 07:37:03 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/11/05 11:59:25 rherveille
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// Fixed wb_ack_o generation bug.
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// Fixed bug in the byte_controller statemachine.
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// Added headers.
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//
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//
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//
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/////////////////////////////////////
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/////////////////////////////////////
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// Bit controller section
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// Bit controller section
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/////////////////////////////////////
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/////////////////////////////////////
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg dscl_oen; // delayed scl_oen
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
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wire slave_wait;
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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begin
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begin
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sSCL <= #1 scl_i;
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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sSDA <= #1 sda_i;
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end
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end
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// delay scl_oen
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always @(posedge clk)
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dscl_oen <= #1 scl_oen;
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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assign slave_wait = scl_oen && !sSCL;
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assign slave_wait = dscl_oen && !sSCL;
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// generate clk enable signal
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// generate clk enable signal
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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