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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.12 2006-09-04 09:08:13 rherveille Exp $
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// $Id: i2c_master_bit_ctrl.v,v 1.13 2009-01-19 20:29:26 rherveille Exp $
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//
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//
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// $Date: 2006-09-04 09:08:13 $
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// $Date: 2009-01-19 20:29:26 $
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// $Revision: 1.12 $
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// $Revision: 1.13 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2006/09/04 09:08:13 rherveille
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// fixed short scl high pulse after clock stretch
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// fixed slave model not returning correct '(n)ack' signal
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//
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// Revision 1.11 2004/05/07 11:02:26 rherveille
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// Revision 1.11 2004/05/07 11:02:26 rherveille
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// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
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// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
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//
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//
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// Revision 1.10 2003/08/09 07:01:33 rherveille
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// Revision 1.10 2003/08/09 07:01:33 rherveille
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// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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wire slave_wait;
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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// state machine variable
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// state machine variable
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reg [16:0] c_state; // synopsys enum_state
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reg [17:0] c_state; // synopsys enum_state
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//
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//
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// module body
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// module body
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//
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//
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dout <= #1 sSDA;
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dout <= #1 sSDA;
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// generate statemachine
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// generate statemachine
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// nxt_state decoder
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// nxt_state decoder
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parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
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parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
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parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
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parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
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parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
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parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
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parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
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parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
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parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
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parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
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parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
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parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
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parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
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parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
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parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
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parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
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parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
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parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
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parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
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parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
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parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
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parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
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parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
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parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
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parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
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parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
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parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
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parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
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parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
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parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
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parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
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parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
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parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
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parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
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parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
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parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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