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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: $
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// Revision 1.14 2009/01/20 10:25:29 rherveille
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// Added clock synchronization logic
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// Fixed slave_wait signal
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//
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// Revision 1.13 2009/01/19 20:29:26 rherveille
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// Revision 1.13 2009/01/19 20:29:26 rherveille
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// Fixed synopsys miss spell (synopsis)
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// Fixed synopsys miss spell (synopsis)
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// Fixed cr[0] register width
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// Fixed cr[0] register width
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// Fixed ! usage instead of ~
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// Fixed ! usage instead of ~
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// Fixed bit controller parameter width to 18bits
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// Fixed bit controller parameter width to 18bits
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// synopsys translate_on
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// synopsys translate_on
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_bit_ctrl(
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module i2c_master_bit_ctrl(
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clk, rst, nReset,
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input clk, // system clock
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clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
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input rst, // synchronous active high reset
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scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
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input nReset, // asynchronous active low reset
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input ena, // core enable signal
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input [15:0] clk_cnt, // clock prescale value
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input [ 3:0] cmd, // command (from byte controller)
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output reg cmd_ack, // command complete acknowledge
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output reg busy, // i2c bus busy
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output reg al, // i2c bus arbitration lost
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input din,
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output reg dout,
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input scl_i, // i2c clock line input
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output scl_o, // i2c clock line output
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output reg scl_oen, // i2c clock line output enable (active low)
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input sda_i, // i2c data line input
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output sda_o, // i2c data line output
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output reg sda_oen // i2c data line output enable (active low)
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);
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);
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//
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// inputs & outputs
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//
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input clk;
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input rst;
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input nReset;
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input ena; // core enable signal
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input [15:0] clk_cnt; // clock prescale value
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input [3:0] cmd;
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output cmd_ack; // command complete acknowledge
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reg cmd_ack;
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output busy; // i2c bus busy
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reg busy;
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output al; // i2c bus arbitration lost
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reg al;
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input din;
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output dout;
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reg dout;
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// I2C lines
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input scl_i; // i2c clock line input
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output scl_o; // i2c clock line output
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output scl_oen; // i2c clock line output enable (active low)
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reg scl_oen;
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input sda_i; // i2c data line input
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output sda_o; // i2c data line output
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output sda_oen; // i2c data line output enable (active low)
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reg sda_oen;
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
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reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
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reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
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reg dSCL, dSDA; // delayed versions of sSCL and sSDA
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reg dSCL, dSDA; // delayed versions of sSCL and sSDA
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reg dscl_oen; // delayed scl_oen
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reg dscl_oen; // delayed scl_oen
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reg sda_chk; // check SDA output (Multi-master arbitration)
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reg sda_chk; // check SDA output (Multi-master arbitration)
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
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reg slave_wait; // slave inserts wait states
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reg slave_wait; // slave inserts wait states
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [13:0] filter_cnt; // clock divider for filter
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// state machine variable
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// state machine variable
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reg [17:0] c_state; // synopsys enum_state
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reg [17:0] c_state; // synopsys enum_state
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//
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//
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Line 191... |
// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// delay scl_oen
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// delay scl_oen
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always @(posedge clk)
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always @(posedge clk)
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dscl_oen <= #1 scl_oen;
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dscl_oen <= #1 scl_oen;
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// slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
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// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
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// slave_wait remains asserted until the slave (other master) releases SCL
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// slave_wait remains asserted until the slave releases SCL
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (!nReset) slave_wait <= 1'b0;
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if (!nReset) slave_wait <= 1'b0;
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else slave_wait = (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
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else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
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// master drives SCL high, but another master pulls it low
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// master drives SCL high, but another master pulls it low
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// master start counting down its low cycle now (clock synchronization)
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// master start counting down its low cycle now (clock synchronization)
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wire scl_sync = dSCL & ~sSCL & scl_oen;
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wire scl_sync = dSCL & ~sSCL & scl_oen;
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// generate clk enable signal
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// generate clk enable signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if(~nReset)
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if(~nReset)
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begin
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begin
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cnt <= #1 16'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if (rst)
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else if (rst || ~|cnt || !ena || scl_sync)
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begin
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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end
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else if ( ~|cnt || !ena || scl_sync)
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begin
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begin
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cnt <= #1 clk_cnt;
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if (slave_wait)
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else if (slave_wait)
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Line 227... |
clk_en <= #1 1'b0;
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clk_en <= #1 1'b0;
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end
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end
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// generate bus status controller
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// generate bus status controller
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reg sta_condition;
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reg sto_condition;
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// synchronize SCL and SDA inputs
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// capture SDA and SCL
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// reduce metastability risc
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// reduce metastability risk
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always @(posedge clk or negedge nReset)
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if (!nReset)
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begin
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cSCL <= #1 2'b00;
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cSDA <= #1 2'b00;
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end
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else if (rst)
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begin
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cSCL <= #1 2'b00;
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cSDA <= #1 2'b00;
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end
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else
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begin
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cSCL <= {cSCL[0],scl_i};
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cSDA <= {cSDA[0],sda_i};
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end
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// filter SCL and SDA signals; (attempt to) remove glitches
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always @(posedge clk or negedge nReset)
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if (!nReset ) filter_cnt <= 14'h0;
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else if (rst || !ena ) filter_cnt <= 14'h0;
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else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
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else filter_cnt <= filter_cnt -1;
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always @(posedge clk or negedge nReset)
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if (!nReset)
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begin
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fSCL <= 3'b111;
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fSDA <= 3'b111;
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end
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else if (rst)
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begin
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fSCL <= 3'b111;
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fSDA <= 3'b111;
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end
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else if (~|filter_cnt)
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begin
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fSCL <= {fSCL[1:0],cSCL[1]};
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fSDA <= {fSDA[1:0],cSDA[1]};
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end
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// generate filtered SCL and SDA signals
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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if (~nReset)
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begin
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begin
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sSCL <= #1 1'b1;
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sSCL <= #1 1'b1;
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sSDA <= #1 1'b1;
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sSDA <= #1 1'b1;
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Line 294... |
dSCL <= #1 1'b1;
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dSCL <= #1 1'b1;
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dSDA <= #1 1'b1;
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dSDA <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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sSCL <= #1 scl_i;
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sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
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sSDA <= #1 sda_i;
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sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
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dSCL <= #1 sSCL;
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dSCL <= #1 sSCL;
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dSDA <= #1 sSDA;
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dSDA <= #1 sSDA;
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end
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end
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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reg sta_condition;
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reg sto_condition;
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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if (~nReset)
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begin
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begin
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sta_condition <= #1 1'b0;
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sta_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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sto_condition <= #1 1'b0;
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begin
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begin
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sta_condition <= #1 ~sSDA & dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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sto_condition <= #1 sSDA & ~dSDA & sSCL;
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end
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end
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// generate i2c bus busy signal
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// generate i2c bus busy signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if(!nReset)
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if (!nReset) busy <= #1 1'b0;
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busy <= #1 1'b0;
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else if (rst ) busy <= #1 1'b0;
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else if (rst)
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else busy <= #1 (sta_condition | busy) & ~sto_condition;
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busy <= #1 1'b0;
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else
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busy <= #1 (sta_condition | busy) & ~sto_condition;
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// generate arbitration lost signal
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// generate arbitration lost signal
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// aribitration lost when:
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// aribitration lost when:
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// 1) master drives SDA high, but the i2c bus is low
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// 1) master drives SDA high, but the i2c bus is low
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// 2) stop detected while not requested
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// 2) stop detected while not requested
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Line 354... |
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
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al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
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// generate dout signal (store SDA on rising edge of SCL)
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// generate dout signal (store SDA on rising edge of SCL)
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always @(posedge clk)
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always @(posedge clk)
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if(sSCL & ~dSCL)
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if (sSCL & ~dSCL) dout <= #1 sSDA;
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dout <= #1 sSDA;
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// generate statemachine
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// generate statemachine
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// nxt_state decoder
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// nxt_state decoder
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parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
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parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
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Line 406... |
case (c_state) // synopsys full_case parallel_case
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case (c_state) // synopsys full_case parallel_case
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// idle state
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// idle state
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idle:
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idle:
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begin
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begin
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case (cmd) // synopsys full_case parallel_case
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case (cmd) // synopsys full_case parallel_case
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`I2C_CMD_START:
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`I2C_CMD_START: c_state <= #1 start_a;
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c_state <= #1 start_a;
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`I2C_CMD_STOP: c_state <= #1 stop_a;
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`I2C_CMD_WRITE: c_state <= #1 wr_a;
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`I2C_CMD_STOP:
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`I2C_CMD_READ: c_state <= #1 rd_a;
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c_state <= #1 stop_a;
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default: c_state <= #1 idle;
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`I2C_CMD_WRITE:
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c_state <= #1 wr_a;
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`I2C_CMD_READ:
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c_state <= #1 rd_a;
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default:
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c_state <= #1 idle;
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endcase
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endcase
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_chk <= #1 1'b0; // don't check SDA output
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sda_chk <= #1 1'b0; // don't check SDA output
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Line 542... |
wr_b:
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wr_b:
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begin
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begin
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c_state <= #1 wr_c;
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c_state <= #1 wr_c;
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 din; // keep SDA
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sda_oen <= #1 din; // keep SDA
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sda_chk <= #1 1'b1; // check SDA output
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sda_chk <= #1 1'b0; // don't check SDA output yet
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// allow some time for SDA and SCL to settle
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end
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end
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wr_c:
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wr_c:
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begin
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begin
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c_state <= #1 wr_d;
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c_state <= #1 wr_d;
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