URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 10 and 11

Rev 10	Rev 11
Line 11...	Line 11...
`module i2c_master_top(`	`module i2c_master_top(`
`wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,`	`wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,`
`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,`	`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,`
`scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );`	`scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );`

	`// parameters`
	`parameter ARST_LVL = 1'b0; // asynchronous reset level`

`//`	`//`
`// inputs & outputs`	`// inputs & outputs`
`//`	`//`

`// wishbone signals`	`// wishbone signals`
Line 71...	Line 74...
`//`	`//`
`// module body`	`// module body`
`//`	`//`

`// generate internal reset`	`// generate internal reset`
wire rst_i = arst_i ^ `I2C_RST_LVL;	`wire rst_i = arst_i ^ ARST_LVL;`

`// generate acknowledge output signal`	`// generate acknowledge output signal`
`assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored`	`assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored`

`// assign DAT_O`	`// assign DAT_O`
Line 211...	Line 214...










`No newline at end of file`	`No newline at end of file`