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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 11 and 13
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| Rev 11 |
Rev 13 |
| Line 61... |
Line 61... |
// done signal: command completed, clear command register
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// done signal: command completed, clear command register
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wire done;
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wire done;
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// core enable signal
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// core enable signal
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wire core_en;
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wire core_en;
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wire ien;
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// status register signals
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// status register signals
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wire irxack;
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wire irxack;
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reg rxack; // received aknowledge from slave
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reg rxack; // received aknowledge from slave
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reg tip; // transfer in progress
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reg tip; // transfer in progress
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| Line 144... |
Line 145... |
wire ack = cr[3];
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wire ack = cr[3];
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wire iack = cr[0];
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wire iack = cr[0];
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// decode control register
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// decode control register
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assign core_en = ctr[7];
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assign core_en = ctr[7];
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assign ien = ctr[6];
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// hookup byte controller block
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// hookup byte controller block
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i2c_master_byte_ctrl byte_controller (
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i2c_master_byte_ctrl byte_controller (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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| Line 199... |
Line 201... |
if (!rst_i)
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if (!rst_i)
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wb_inta_o <= #1 1'b0;
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wb_inta_o <= #1 1'b0;
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else if (wb_rst_i)
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else if (wb_rst_i)
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wb_inta_o <= #1 1'b0;
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wb_inta_o <= #1 1'b0;
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else
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else
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wb_inta_o <= #1 irq_flag && ctr[6]; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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// assign status register bits
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// assign status register bits
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assign sr[7] = rxack;
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assign sr[7] = rxack;
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assign sr[6] = i2c_busy;
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assign sr[6] = i2c_busy;
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assign sr[5:2] = 4'h0; // reserved
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assign sr[5:2] = 4'h0; // reserved
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