| Line 1... |
Line 1... |
|
/////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// WISHBONE rev.B2 compliant I2C Master controller Top-level ////
|
|
//// ////
|
|
//// ////
|
|
//// Author: Richard Herveille ////
|
|
//// richard@asics.ws ////
|
|
//// www.asics.ws ////
|
|
//// ////
|
|
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
|
//// ////
|
|
/////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2001 Richard Herveille ////
|
|
//// richard@asics.ws ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer.////
|
|
//// ////
|
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
|
//// ////
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
// CVS Log
|
|
//
|
|
// $Id: i2c_master_top.v,v 1.4 2001-11-05 11:59:25 rherveille Exp $
|
|
//
|
|
// $Date: 2001-11-05 11:59:25 $
|
|
// $Revision: 1.4 $
|
|
// $Author: rherveille $
|
|
// $Locker: $
|
|
// $State: Exp $
|
//
|
//
|
// WISHBONE revB2 compiant I2C master core
|
// Change History:
|
//
|
// $Log: not supported by cvs2svn $
|
// author: Richard Herveille
|
|
// rev. 0.1 26-08-2001. Iinitial Verilog release
|
|
//
|
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "i2c_master_defines.v"
|
`include "i2c_master_defines.v"
|
|
|
module i2c_master_top(
|
module i2c_master_top(
|
| Line 91... |
Line 134... |
3'b010: wb_dat_o = ctr;
|
3'b010: wb_dat_o = ctr;
|
3'b011: wb_dat_o = rxr; // write is transmit register (txr)
|
3'b011: wb_dat_o = rxr; // write is transmit register (txr)
|
3'b100: wb_dat_o = sr; // write is command register (cr)
|
3'b100: wb_dat_o = sr; // write is command register (cr)
|
3'b101: wb_dat_o = txr;
|
3'b101: wb_dat_o = txr;
|
3'b110: wb_dat_o = cr;
|
3'b110: wb_dat_o = cr;
|
|
3'b111: wb_dat_o = 0; // reserved
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// generate registers
|
// generate registers
|
