URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 14 and 16

Rev 14	Rev 16
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: i2c_master_top.v,v 1.4 2001-11-05 11:59:25 rherveille Exp $`	`// $Id: i2c_master_top.v,v 1.5 2001-11-10 10:52:55 rherveille Exp $`
`//`	`//`
`// $Date: 2001-11-05 11:59:25 $`	`// $Date: 2001-11-10 10:52:55 $`
`// $Revision: 1.4 $`	`// $Revision: 1.5 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
Line 143...	Line 143...

`// generate registers`	`// generate registers`
`always@(posedge wb_clk_i or negedge rst_i)`	`always@(posedge wb_clk_i or negedge rst_i)`
`if (!rst_i)`	`if (!rst_i)`
`begin`	`begin`
`prer <= #1 16'h0;`	`prer <= #1 16'hffff;`
`ctr <= #1 8'h0;`	`ctr <= #1 8'h0;`
`txr <= #1 8'h0;`	`txr <= #1 8'h0;`
`cr <= #1 8'h0;`	`cr <= #1 8'h0;`
`end`	`end`
`else if (wb_rst_i)`	`else if (wb_rst_i)`
`begin`	`begin`
`prer <= #1 16'h0;`	`prer <= #1 16'hffff;`
`ctr <= #1 8'h0;`	`ctr <= #1 8'h0;`
`txr <= #1 8'h0;`	`txr <= #1 8'h0;`
`cr <= #1 8'h0;`	`cr <= #1 8'h0;`
`end`	`end`
`else`	`else`
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