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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master controller Top-level ////
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//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_top.v,v 1.5 2001-11-10 10:52:55 rherveille Exp $
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// $Id: i2c_master_top.v,v 1.6 2002-11-30 22:24:40 rherveille Exp $
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//
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//
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// $Date: 2001-11-10 10:52:55 $
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// $Date: 2002-11-30 22:24:40 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/11/10 10:52:55 rherveille
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// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_top(
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module i2c_master_top(
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wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
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input wb_rst_i; // synchronous active high reset
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input wb_rst_i; // synchronous active high reset
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input arst_i; // asynchronous reset
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input arst_i; // asynchronous reset
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input [2:0] wb_adr_i; // lower address bits
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input [2:0] wb_adr_i; // lower address bits
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input [7:0] wb_dat_i; // databus input
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input [7:0] wb_dat_i; // databus input
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output [7:0] wb_dat_o; // databus output
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output [7:0] wb_dat_o; // databus output
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reg [7:0] wb_dat_o;
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input wb_we_i; // write enable input
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input wb_we_i; // write enable input
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input wb_stb_i; // stobe/core select signal
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input wb_stb_i; // stobe/core select signal
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input wb_cyc_i; // valid bus cycle input
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input wb_cyc_i; // valid bus cycle input
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output wb_ack_o; // bus cycle acknowledge output
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output wb_ack_o; // bus cycle acknowledge output
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output wb_inta_o; // interrupt request signal output
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output wb_inta_o; // interrupt request signal output
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reg [7:0] wb_dat_o;
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reg wb_ack_o;
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reg wb_inta_o;
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reg wb_inta_o;
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// I2C signals
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// I2C signals
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// i2c clock line
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// i2c clock line
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input scl_pad_i; // SCL-line input
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input scl_pad_i; // SCL-line input
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output scl_pad_o; // SCL-line output (always 1'b0)
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output scl_pad_o; // SCL-line output (always 1'b0)
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output scl_padoen_o; // SCL-line output enable (active low)
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output scl_padoen_o; // SCL-line output enable (active low)
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// i2c data line
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// i2c data line
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input sda_pad_i; // SDA-line input
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input sda_pad_i; // SDA-line input
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output sda_pad_o; // SDA-line output (always 1'b0)
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output sda_pad_o; // SDA-line output (always 1'b0)
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output sda_padoen_o; // SDA-line output enable (active low)
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output sda_padoen_o; // SDA-line output enable (active low)
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// generate internal reset
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// generate internal reset
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wire rst_i = arst_i ^ ARST_LVL;
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wire rst_i = arst_i ^ ARST_LVL;
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// generate acknowledge output signal
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// generate acknowledge output signal
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assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored
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always @(posedge wb_clk_i)
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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// assign DAT_O
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// assign DAT_O
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always@(wb_adr_i or prer or ctr or txr or cr or rxr or sr)
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always @(posedge wb_clk_i)
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begin
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begin
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case (wb_adr_i) // synopsis full_case parallel_case
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case (wb_adr_i) // synopsis full_case parallel_case
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3'b000: wb_dat_o = prer[ 7:0];
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3'b000: wb_dat_o = prer[ 7:0];
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3'b001: wb_dat_o = prer[15:8];
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3'b001: wb_dat_o = prer[15:8];
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3'b010: wb_dat_o = ctr;
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3'b010: wb_dat_o = ctr;
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irq_flag <= #1 1'b0;
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irq_flag <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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rxack <= #1 irxack;
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rxack <= #1 irxack;
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tip <= #1 (rd || wr);
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tip <= #1 (rd | wr);
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irq_flag <= #1 (done || irq_flag) && !iack; // interrupt request flag is always generated
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irq_flag <= #1 (done | irq_flag) & ~iack; // interrupt request flag is always generated
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end
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end
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// generate interrupt request signals
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// generate interrupt request signals
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always@(posedge wb_clk_i or negedge rst_i)
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always@(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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assign sr[1] = tip;
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assign sr[1] = tip;
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assign sr[0] = irq_flag;
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assign sr[0] = irq_flag;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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