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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_top.v,v 1.6 2002-11-30 22:24:40 rherveille Exp $
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// $Id: i2c_master_top.v,v 1.7 2002-12-26 15:02:32 rherveille Exp $
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//
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//
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// $Date: 2002-11-30 22:24:40 $
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// $Date: 2002-12-26 15:02:32 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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//
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// Revision 1.5 2001/11/10 10:52:55 rherveille
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// Revision 1.5 2001/11/10 10:52:55 rherveille
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// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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Line 124... |
wire irxack;
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wire irxack;
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reg rxack; // received aknowledge from slave
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reg rxack; // received aknowledge from slave
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reg tip; // transfer in progress
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reg tip; // transfer in progress
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reg irq_flag; // interrupt pending flag
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reg irq_flag; // interrupt pending flag
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wire i2c_busy; // bus busy (start signal detected)
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wire i2c_busy; // bus busy (start signal detected)
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wire i2c_al; // i2c bus arbitration lost
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reg al; // status register arbitration lost bit
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//
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//
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// module body
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// module body
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//
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//
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// generate internal reset
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// generate internal reset
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wire rst_i = arst_i ^ ARST_LVL;
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wire rst_i = arst_i ^ ARST_LVL;
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// generate wishbone signals
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wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
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// generate acknowledge output signal
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// generate acknowledge output signal
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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// assign DAT_O
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// assign DAT_O
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Line 156... |
3'b110: wb_dat_o = cr;
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3'b110: wb_dat_o = cr;
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3'b111: wb_dat_o = 0; // reserved
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3'b111: wb_dat_o = 0; // reserved
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endcase
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endcase
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end
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end
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// generate registers
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// generate registers
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always @(posedge wb_clk_i or negedge rst_i)
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always @(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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begin
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begin
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prer <= #1 16'hffff;
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prer <= #1 16'hffff;
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Line 173... |
ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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cr <= #1 8'h0;
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cr <= #1 8'h0;
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end
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end
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else
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else
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if (wb_cyc_i && wb_stb_i && wb_we_i)
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if (wb_wacc)
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begin
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case (wb_adr_i) // synopsis full_case parallel_case
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if (!wb_adr_i[2])
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3'b000 : prer [ 7:0] <= #1 wb_dat_i;
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case (wb_adr_i[1:0]) // synopsis full_case parallel_case
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3'b001 : prer [15:8] <= #1 wb_dat_i;
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2'b00 : prer [ 7:0] <= #1 wb_dat_i;
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3'b010 : ctr <= #1 wb_dat_i;
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2'b01 : prer [15:8] <= #1 wb_dat_i;
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3'b011 : txr <= #1 wb_dat_i;
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2'b10 : ctr <= #1 wb_dat_i;
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2'b11 : txr <= #1 wb_dat_i;
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endcase
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endcase
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else
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if (core_en && (wb_adr_i[1:0] == 2'b00) ) // only take new commands when i2c core enabled, pending commands are finished
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// generate command register (special case)
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always @(posedge wb_clk_i or negedge rst_i)
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if (~rst_i)
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cr <= #1 8'h0;
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else if (wb_rst_i)
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cr <= #1 8'h0;
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else if (wb_wacc)
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begin
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if (core_en & (wb_adr_i == 3'b100) )
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cr <= #1 wb_dat_i;
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cr <= #1 wb_dat_i;
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end
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end
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else
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else
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begin
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begin
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if (done)
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if (done | i2c_al)
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cr[7:4] <= #1 4'h0; // clear command bits when done
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cr[7:4] <= #1 4'h0; // clear command bits when done
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// or when aribitration lost
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cr[2:1] <= #1 2'b00; // reserved bits
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cr[2:1] <= #1 2'b0; // reserved bits
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cr[0] <= #1 cr[0] && irq_flag; // clear when irq_flag cleared
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cr[0] <= #1 cr[0] & irq_flag; // clear when irq_flag is cleared
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end
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end
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// decode command register
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// decode command register
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wire sta = cr[7];
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wire sta = cr[7];
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Line 231... |
.din ( txr ),
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.din ( txr ),
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.cmd_ack ( done ),
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.cmd_ack ( done ),
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.ack_out ( irxack ),
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.ack_out ( irxack ),
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.dout ( rxr ),
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.dout ( rxr ),
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.i2c_busy ( i2c_busy ),
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.i2c_busy ( i2c_busy ),
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.i2c_al ( i2c_al ),
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.scl_i ( scl_pad_i ),
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.scl_i ( scl_pad_i ),
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.scl_o ( scl_pad_o ),
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.scl_o ( scl_pad_o ),
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.scl_oen ( scl_padoen_o ),
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.scl_oen ( scl_padoen_o ),
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.sda_i ( sda_pad_i ),
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.sda_i ( sda_pad_i ),
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.sda_o ( sda_pad_o ),
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.sda_o ( sda_pad_o ),
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.sda_oen ( sda_padoen_o )
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.sda_oen ( sda_padoen_o )
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);
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);
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// status register block + interrupt request signal
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// status register block + interrupt request signal
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always @(posedge wb_clk_i or negedge rst_i)
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always @(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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begin
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begin
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al <= #1 1'b0;
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rxack <= #1 1'b0;
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rxack <= #1 1'b0;
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tip <= #1 1'b0;
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tip <= #1 1'b0;
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irq_flag <= #1 1'b0;
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irq_flag <= #1 1'b0;
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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begin
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begin
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al <= #1 1'b0;
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rxack <= #1 1'b0;
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rxack <= #1 1'b0;
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tip <= #1 1'b0;
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tip <= #1 1'b0;
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irq_flag <= #1 1'b0;
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irq_flag <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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al <= #1 i2c_al | (al & ~sta);
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rxack <= #1 irxack;
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rxack <= #1 irxack;
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tip <= #1 (rd | wr);
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tip <= #1 (rd | wr);
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irq_flag <= #1 (done | irq_flag) & ~iack; // interrupt request flag is always generated
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irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
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end
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end
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// generate interrupt request signals
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// generate interrupt request signals
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always @(posedge wb_clk_i or negedge rst_i)
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always @(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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Line 276... |
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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// assign status register bits
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// assign status register bits
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assign sr[7] = rxack;
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assign sr[7] = rxack;
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assign sr[6] = i2c_busy;
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assign sr[6] = i2c_busy;
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assign sr[5:2] = 4'h0; // reserved
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assign sr[5] = al;
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assign sr[4:2] = 3'h0; // reserved
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assign sr[1] = tip;
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assign sr[1] = tip;
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assign sr[0] = irq_flag;
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assign sr[0] = irq_flag;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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