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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 29 and 30
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| Rev 29 |
Rev 30 |
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Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_top.v,v 1.7 2002-12-26 15:02:32 rherveille Exp $
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// $Id: i2c_master_top.v,v 1.8 2002-12-26 16:05:12 rherveille Exp $
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//
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//
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// $Date: 2002-12-26 15:02:32 $
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// $Date: 2002-12-26 16:05:12 $
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// $Revision: 1.7 $
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// $Revision: 1.8 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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//
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// Revision 1.6 2002/11/30 22:24:40 rherveille
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// Revision 1.6 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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// Cleaned up code
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//
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//
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// Revision 1.5 2001/11/10 10:52:55 rherveille
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// Revision 1.5 2001/11/10 10:52:55 rherveille
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// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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begin
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begin
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if (done | i2c_al)
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if (done | i2c_al)
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cr[7:4] <= #1 4'h0; // clear command bits when done
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cr[7:4] <= #1 4'h0; // clear command bits when done
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// or when aribitration lost
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// or when aribitration lost
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cr[2:1] <= #1 2'b0; // reserved bits
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cr[2:1] <= #1 2'b0; // reserved bits
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cr[0] <= #1 cr[0] & irq_flag; // clear when irq_flag is cleared
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cr[0] <= #1 2'b0; // clear IRQ_ACK bit
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end
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end
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// decode command register
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// decode command register
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wire sta = cr[7];
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wire sta = cr[7];
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