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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 30 and 33
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| Rev 30 |
Rev 33 |
| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_top.v,v 1.8 2002-12-26 16:05:12 rherveille Exp $
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// $Id: i2c_master_top.v,v 1.9 2003-01-09 16:44:45 rherveille Exp $
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//
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//
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// $Date: 2002-12-26 16:05:12 $
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// $Date: 2003-01-09 16:44:45 $
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// $Revision: 1.8 $
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// $Revision: 1.9 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/12/26 16:05:12 rherveille
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// Small code simplifications
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//
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// Revision 1.7 2002/12/26 15:02:32 rherveille
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// Revision 1.7 2002/12/26 15:02:32 rherveille
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// Core is now a Multimaster I2C controller
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// Core is now a Multimaster I2C controller
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//
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//
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// Revision 1.6 2002/11/30 22:24:40 rherveille
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// Revision 1.6 2002/11/30 22:24:40 rherveille
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// Cleaned up code
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// Cleaned up code
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| Line 166... |
Line 169... |
if (!rst_i)
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if (!rst_i)
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begin
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begin
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prer <= #1 16'hffff;
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prer <= #1 16'hffff;
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ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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cr <= #1 8'h0;
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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begin
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begin
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prer <= #1 16'hffff;
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prer <= #1 16'hffff;
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ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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cr <= #1 8'h0;
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end
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end
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else
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else
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if (wb_wacc)
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if (wb_wacc)
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case (wb_adr_i) // synopsis full_case parallel_case
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case (wb_adr_i) // synopsis full_case parallel_case
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3'b000 : prer [ 7:0] <= #1 wb_dat_i;
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3'b000 : prer [ 7:0] <= #1 wb_dat_i;
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