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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: i2c_master_top.v,v 1.10 2003-09-01 10:34:38 rherveille Exp $
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// $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $
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//
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//
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// $Date: 2003-09-01 10:34:38 $
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// $Date: 2005-02-27 09:26:24 $
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// $Revision: 1.10 $
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// $Revision: 1.11 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/09/01 10:34:38 rherveille
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// Fix a blocking vs. non-blocking error in the wb_dat output mux.
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//
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// Revision 1.9 2003/01/09 16:44:45 rherveille
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// Revision 1.9 2003/01/09 16:44:45 rherveille
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// Fixed a bug in the Command Register declaration.
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// Fixed a bug in the Command Register declaration.
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//
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//
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// Revision 1.8 2002/12/26 16:05:12 rherveille
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// Revision 1.8 2002/12/26 16:05:12 rherveille
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// Small code simplifications
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// Small code simplifications
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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// assign DAT_O
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// assign DAT_O
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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begin
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begin
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case (wb_adr_i) // synopsis full_case parallel_case
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case (wb_adr_i) // synopsis parallel_case
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3'b000: wb_dat_o <= #1 prer[ 7:0];
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3'b000: wb_dat_o <= #1 prer[ 7:0];
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3'b001: wb_dat_o <= #1 prer[15:8];
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3'b001: wb_dat_o <= #1 prer[15:8];
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3'b010: wb_dat_o <= #1 ctr;
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3'b010: wb_dat_o <= #1 ctr;
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3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
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3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
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3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
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3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
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ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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end
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end
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else
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else
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if (wb_wacc)
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if (wb_wacc)
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case (wb_adr_i) // synopsis full_case parallel_case
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case (wb_adr_i) // synopsis parallel_case
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3'b000 : prer [ 7:0] <= #1 wb_dat_i;
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3'b000 : prer [ 7:0] <= #1 wb_dat_i;
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3'b001 : prer [15:8] <= #1 wb_dat_i;
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3'b001 : prer [15:8] <= #1 wb_dat_i;
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3'b010 : ctr <= #1 wb_dat_i;
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3'b010 : ctr <= #1 wb_dat_i;
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3'b011 : txr <= #1 wb_dat_i;
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3'b011 : txr <= #1 wb_dat_i;
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default: ;
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endcase
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endcase
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// generate command register (special case)
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// generate command register (special case)
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always @(posedge wb_clk_i or negedge rst_i)
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always @(posedge wb_clk_i or negedge rst_i)
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if (~rst_i)
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if (~rst_i)
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