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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 55 and 62

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/////////////////////////////////////////////////////////////////////
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//  CVS Log
//  CVS Log
//
//
//  $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $
//  $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $
//
//
//  $Date: 2005-02-27 09:26:24 $
//  $Date: 2009-01-19 20:29:26 $
//  $Revision: 1.11 $
//  $Revision: 1.12 $
//  $Author: rherveille $
//  $Author: rherveille $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.11  2005/02/27 09:26:24  rherveille
 
//               Fixed register overwrite issue.
 
//               Removed full_case pragma, replaced it by a default statement.
 
//
//               Revision 1.10  2003/09/01 10:34:38  rherveille
//               Revision 1.10  2003/09/01 10:34:38  rherveille
//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
//
//               Revision 1.9  2003/01/09 16:44:45  rherveille
//               Revision 1.9  2003/01/09 16:44:45  rherveille
//               Fixed a bug in the Command Register declaration.
//               Fixed a bug in the Command Register declaration.
Line 156... Line 160...
          wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
          wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
 
 
        // assign DAT_O
        // assign DAT_O
        always @(posedge wb_clk_i)
        always @(posedge wb_clk_i)
        begin
        begin
          case (wb_adr_i) // synopsis parallel_case
          case (wb_adr_i) // synopsys parallel_case
            3'b000: wb_dat_o <= #1 prer[ 7:0];
            3'b000: wb_dat_o <= #1 prer[ 7:0];
            3'b001: wb_dat_o <= #1 prer[15:8];
            3'b001: wb_dat_o <= #1 prer[15:8];
            3'b010: wb_dat_o <= #1 ctr;
            3'b010: wb_dat_o <= #1 ctr;
            3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
            3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
            3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
            3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
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                ctr  <= #1  8'h0;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
                txr  <= #1  8'h0;
            end
            end
          else
          else
            if (wb_wacc)
            if (wb_wacc)
              case (wb_adr_i) // synopsis parallel_case
              case (wb_adr_i) // synopsys parallel_case
                 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
                 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
                 3'b001 : prer [15:8] <= #1 wb_dat_i;
                 3'b001 : prer [15:8] <= #1 wb_dat_i;
                 3'b010 : ctr         <= #1 wb_dat_i;
                 3'b010 : ctr         <= #1 wb_dat_i;
                 3'b011 : txr         <= #1 wb_dat_i;
                 3'b011 : txr         <= #1 wb_dat_i;
                 default: ;
                 default: ;
              endcase
              endcase
 
 
        // generate command register (special case)
        // generate command register (special case)
        always @(posedge wb_clk_i or negedge rst_i)
        always @(posedge wb_clk_i or negedge rst_i)
          if (~rst_i)
          if (!rst_i)
            cr <= #1 8'h0;
            cr <= #1 8'h0;
          else if (wb_rst_i)
          else if (wb_rst_i)
            cr <= #1 8'h0;
            cr <= #1 8'h0;
          else if (wb_wacc)
          else if (wb_wacc)
            begin
            begin
Line 209... Line 213...
            begin
            begin
                if (done | i2c_al)
                if (done | i2c_al)
                  cr[7:4] <= #1 4'h0;           // clear command bits when done
                  cr[7:4] <= #1 4'h0;           // clear command bits when done
                                                // or when aribitration lost
                                                // or when aribitration lost
                cr[2:1] <= #1 2'b0;             // reserved bits
                cr[2:1] <= #1 2'b0;             // reserved bits
                cr[0]   <= #1 2'b0;             // clear IRQ_ACK bit
                cr[0]   <= #1 1'b0;             // clear IRQ_ACK bit
            end
            end
 
 
 
 
        // decode command register
        // decode command register
        wire sta  = cr[7];
        wire sta  = cr[7];

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