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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.1 2001-11-05 12:02:33 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.2 2002-06-15 07:37:04 rherveille Exp $
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--
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--
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-- $Date: 2001-11-05 12:02:33 $
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-- $Date: 2002-06-15 07:37:04 $
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-- $Revision: 1.1 $
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-- $Revision: 1.2 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Code updated, is now up-to-date to doc. rev.0.4.
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-- Added headers.
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--
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--
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--
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-------------------------------------
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-------------------------------------
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-- Bit controller section
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-- Bit controller section
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type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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signal c_state : states;
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signal c_state : states;
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal clk_en, slave_wait :std_logic; -- clock generation signals
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signal clk_en, slave_wait :std_logic; -- clock generation signals
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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sSCL <= scl_i after Tcq;
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sSCL <= scl_i after Tcq;
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sSDA <= sda_i after Tcq;
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sSDA <= sda_i after Tcq;
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end if;
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end if;
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end process synch_SCL_SDA;
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end process synch_SCL_SDA;
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-- delay scl_oen
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process (clk)
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begin
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if (clk'event and clk = '1') then
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dscl_oen <= iscl_oen after Tcq;
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end if;
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end process;
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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slave_wait <= iscl_oen and not sSCL;
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slave_wait <= dscl_oen and not sSCL;
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-- generate clk enable signal
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-- generate clk enable signal
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gen_clken: process(clk, nReset)
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gen_clken: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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