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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 22 and 24

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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.2 2002-06-15 07:37:04 rherveille Exp $
--  $Id: i2c_master_bit_ctrl.vhd,v 1.3 2002-10-30 18:09:53 rherveille Exp $
--
--
--  $Date: 2002-06-15 07:37:04 $
--  $Date: 2002-10-30 18:09:53 $
--  $Revision: 1.2 $
--  $Revision: 1.3 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.2  2002/06/15 07:37:04  rherveille
 
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
 
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Added headers.
--               Added headers.
--
--
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        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
 
 
        type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
 
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
        signal c_state : states;
        signal c_state : states;
 
 
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
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        -- generate statemachine
        -- generate statemachine
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
                variable nxt_state : states;
                variable nxt_state : states;
                variable icmd_ack, store_sda : std_logic;
                variable icmd_ack, store_sda : std_logic;
        begin
        begin
 
 
                nxt_state := c_state;
                nxt_state := c_state;
 
 
                icmd_ack := '0'; -- default no acknowledge
                icmd_ack := '0'; -- default no acknowledge
 
 
                store_sda := '0';
                store_sda := '0';
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                        when start_c =>
                        when start_c =>
                                nxt_state := start_d;
                                nxt_state := start_d;
 
 
                        when start_d =>
                        when start_d =>
 
                nxt_state := start_e;
 
 
 
              when start_e =>
                                nxt_state := idle;
                                nxt_state := idle;
                                icmd_ack := '1'; -- command completed
                                icmd_ack := '1'; -- command completed
 
 
                        -- stop
                        -- stop
                        when stop_a =>
                        when stop_a =>
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                        when stop_b =>
                        when stop_b =>
                                nxt_state := stop_c;
                                nxt_state := stop_c;
 
 
                        when stop_c =>
                        when stop_c =>
 
                nxt_state := stop_d;
 
 
 
              when stop_d =>
                                nxt_state := idle;
                                nxt_state := idle;
                                icmd_ack := '1'; -- command completed
                                icmd_ack := '1'; -- command completed
 
 
                        -- read
                        -- read
                        when rd_a =>
                        when rd_a =>
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                elsif (clk'event and clk = '1') then
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                        if (rst = '1') then
                                c_state <= idle after Tcq;
                                c_state <= idle after Tcq;
                                cmd_ack <= '0' after Tcq;
                                cmd_ack <= '0' after Tcq;
                                Dout    <= '0' after Tcq;
                                Dout    <= '0' after Tcq;
                        else
              elsif (clk_en = '1') then
                                if (clk_en = '1') then
 
                                        c_state <= nxt_state after Tcq;
                                        c_state <= nxt_state after Tcq;
 
 
                                        if (store_sda = '1') then
                                        if (store_sda = '1') then
                                                dout <= sSDA after Tcq;
                                                dout <= sSDA after Tcq;
                                        end if;
                                        end if;
                                end if;
                                end if;
 
 
                                cmd_ack <= icmd_ack and clk_en;
                                cmd_ack <= icmd_ack and clk_en;
                        end if;
                        end if;
                end if;
 
        end process nxt_state_decoder;
        end process nxt_state_decoder;
 
 
        --
        --
        -- convert states to SCL and SDA signals
        -- convert states to SCL and SDA signals
        --
        --
        output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
        output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
                variable iscl, isda : std_logic;
                variable iscl, isda : std_logic;
        begin
        begin
                case (c_state) is
                case (c_state) is
 
              -- idle
                        when idle =>
                        when idle =>
                                iscl := iscl_oen; -- keep SCL in same state
                                iscl := iscl_oen; -- keep SCL in same state
                                isda := isda_oen; -- keep SDA in same state
                                isda := isda_oen; -- keep SDA in same state
 
 
                        -- start
                        -- start
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                                iscl := '1';    -- set SCL high
                                iscl := '1';    -- set SCL high
                                isda := '1'; -- keep SDA high
                                isda := '1'; -- keep SDA high
 
 
                        when start_c =>
                        when start_c =>
                                iscl := '1';    -- keep SCL high
                                iscl := '1';    -- keep SCL high
                                isda := '0'; -- sel SDA low
                isda := '0'; -- set SDA low
 
 
                        when start_d =>
                        when start_d =>
 
                iscl := '1'; -- keep SCL high
 
                isda := '0'; -- keep SDA low
 
 
 
              when start_e =>
                                iscl := '0'; -- set SCL low
                                iscl := '0'; -- set SCL low
                                isda := '0'; -- keep SDA low
                                isda := '0'; -- keep SDA low
 
 
                        -- stop
                        -- stop
                        when stop_a =>
                        when stop_a =>
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                                iscl := '1'; -- set SCL high
                                iscl := '1'; -- set SCL high
                                isda := '0'; -- keep SDA low
                                isda := '0'; -- keep SDA low
 
 
                        when stop_c =>
                        when stop_c =>
                                iscl := '1'; -- keep SCL high
                                iscl := '1'; -- keep SCL high
 
                 isda := '0'; -- keep SDA low
 
 
 
              when stop_d =>
 
                iscl := '1'; -- keep SCL high
                                isda := '1'; -- set SDA high
                                isda := '1'; -- set SDA high
 
 
                        -- write
                        -- write
                        when wr_a =>
                        when wr_a =>
                                iscl := '0';     -- keep SCL low
                                iscl := '0';     -- keep SCL low
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                        isda_oen <= '1' after Tcq;
                        isda_oen <= '1' after Tcq;
                elsif (clk'event and clk = '1') then
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                        if (rst = '1') then
                                iscl_oen <= '1' after Tcq;
                                iscl_oen <= '1' after Tcq;
                                isda_oen <= '1' after Tcq;
                                isda_oen <= '1' after Tcq;
                        else
              elsif (clk_en = '1') then
                                if (clk_en = '1') then
 
                                        iscl_oen <= iscl after Tcq;
                                        iscl_oen <= iscl after Tcq;
                                        isda_oen <= isda after Tcq;
                                        isda_oen <= isda after Tcq;
                                end if;
                                end if;
                        end if;
                        end if;
                end if;
 
        end process output_decoder;
        end process output_decoder;
 
 
        -- assign outputs
        -- assign outputs
        scl_o   <= '0';
        scl_o   <= '0';
        scl_oen <= iscl_oen;
        scl_oen <= iscl_oen;

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