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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.2 2002-06-15 07:37:04 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.3 2002-10-30 18:09:53 rherveille Exp $
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--
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--
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-- $Date: 2002-06-15 07:37:04 $
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-- $Date: 2002-10-30 18:09:53 $
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-- $Revision: 1.2 $
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-- $Revision: 1.3 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2002/06/15 07:37:04 rherveille
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-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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--
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Code updated, is now up-to-date to doc. rev.0.4.
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-- Code updated, is now up-to-date to doc. rev.0.4.
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-- Added headers.
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-- Added headers.
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--
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--
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Line 134... |
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
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constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
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constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
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constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
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constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
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constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
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constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
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constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
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type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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type states is (idle, start_a, start_b, start_c, start_d, start_e,
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stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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signal c_state : states;
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signal c_state : states;
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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Line 236... |
-- generate statemachine
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-- generate statemachine
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nxt_state_decoder : process (clk, nReset, c_state, cmd)
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nxt_state_decoder : process (clk, nReset, c_state, cmd)
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variable nxt_state : states;
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variable nxt_state : states;
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variable icmd_ack, store_sda : std_logic;
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variable icmd_ack, store_sda : std_logic;
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begin
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begin
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nxt_state := c_state;
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nxt_state := c_state;
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icmd_ack := '0'; -- default no acknowledge
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icmd_ack := '0'; -- default no acknowledge
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store_sda := '0';
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store_sda := '0';
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Line 273... |
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when start_c =>
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when start_c =>
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nxt_state := start_d;
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nxt_state := start_d;
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when start_d =>
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when start_d =>
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nxt_state := start_e;
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when start_e =>
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nxt_state := idle;
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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icmd_ack := '1'; -- command completed
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-- stop
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-- stop
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when stop_a =>
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when stop_a =>
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Line 287... |
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when stop_b =>
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when stop_b =>
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nxt_state := stop_c;
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nxt_state := stop_c;
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when stop_c =>
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when stop_c =>
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nxt_state := stop_d;
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when stop_d =>
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nxt_state := idle;
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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icmd_ack := '1'; -- command completed
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-- read
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-- read
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when rd_a =>
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when rd_a =>
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Line 334... |
elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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c_state <= idle after Tcq;
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c_state <= idle after Tcq;
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cmd_ack <= '0' after Tcq;
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cmd_ack <= '0' after Tcq;
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Dout <= '0' after Tcq;
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Dout <= '0' after Tcq;
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else
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elsif (clk_en = '1') then
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if (clk_en = '1') then
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c_state <= nxt_state after Tcq;
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c_state <= nxt_state after Tcq;
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if (store_sda = '1') then
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if (store_sda = '1') then
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dout <= sSDA after Tcq;
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dout <= sSDA after Tcq;
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end if;
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end if;
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end if;
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end if;
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cmd_ack <= icmd_ack and clk_en;
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cmd_ack <= icmd_ack and clk_en;
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end if;
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end if;
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end if;
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end process nxt_state_decoder;
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end process nxt_state_decoder;
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--
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--
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-- convert states to SCL and SDA signals
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-- convert states to SCL and SDA signals
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--
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--
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output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
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output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
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variable iscl, isda : std_logic;
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variable iscl, isda : std_logic;
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begin
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begin
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case (c_state) is
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case (c_state) is
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-- idle
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when idle =>
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when idle =>
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iscl := iscl_oen; -- keep SCL in same state
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iscl := iscl_oen; -- keep SCL in same state
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isda := isda_oen; -- keep SDA in same state
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isda := isda_oen; -- keep SDA in same state
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-- start
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-- start
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Line 369... |
iscl := '1'; -- set SCL high
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iscl := '1'; -- set SCL high
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isda := '1'; -- keep SDA high
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isda := '1'; -- keep SDA high
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when start_c =>
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when start_c =>
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iscl := '1'; -- keep SCL high
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iscl := '1'; -- keep SCL high
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isda := '0'; -- sel SDA low
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isda := '0'; -- set SDA low
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when start_d =>
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when start_d =>
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iscl := '1'; -- keep SCL high
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isda := '0'; -- keep SDA low
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when start_e =>
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iscl := '0'; -- set SCL low
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iscl := '0'; -- set SCL low
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isda := '0'; -- keep SDA low
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isda := '0'; -- keep SDA low
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-- stop
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-- stop
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when stop_a =>
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when stop_a =>
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Line 390... |
iscl := '1'; -- set SCL high
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iscl := '1'; -- set SCL high
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isda := '0'; -- keep SDA low
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isda := '0'; -- keep SDA low
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when stop_c =>
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when stop_c =>
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iscl := '1'; -- keep SCL high
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iscl := '1'; -- keep SCL high
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isda := '0'; -- keep SDA low
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when stop_d =>
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iscl := '1'; -- keep SCL high
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isda := '1'; -- set SDA high
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isda := '1'; -- set SDA high
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-- write
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-- write
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when wr_a =>
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when wr_a =>
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iscl := '0'; -- keep SCL low
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iscl := '0'; -- keep SCL low
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Line 439... |
isda_oen <= '1' after Tcq;
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isda_oen <= '1' after Tcq;
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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iscl_oen <= '1' after Tcq;
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iscl_oen <= '1' after Tcq;
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isda_oen <= '1' after Tcq;
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isda_oen <= '1' after Tcq;
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else
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elsif (clk_en = '1') then
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if (clk_en = '1') then
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iscl_oen <= iscl after Tcq;
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iscl_oen <= iscl after Tcq;
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isda_oen <= isda after Tcq;
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isda_oen <= isda after Tcq;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process output_decoder;
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end process output_decoder;
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-- assign outputs
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-- assign outputs
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scl_o <= '0';
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scl_o <= '0';
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scl_oen <= iscl_oen;
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scl_oen <= iscl_oen;
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