| Line 35... |
Line 35... |
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
-- CVS Log
|
-- CVS Log
|
--
|
--
|
-- $Id: i2c_master_bit_ctrl.vhd,v 1.4 2002-11-30 22:24:37 rherveille Exp $
|
-- $Id: i2c_master_bit_ctrl.vhd,v 1.5 2002-12-26 16:05:47 rherveille Exp $
|
--
|
--
|
-- $Date: 2002-11-30 22:24:37 $
|
-- $Date: 2002-12-26 16:05:47 $
|
-- $Revision: 1.4 $
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-- $Revision: 1.5 $
|
-- $Author: rherveille $
|
-- $Author: rherveille $
|
-- $Locker: $
|
-- $Locker: $
|
-- $State: Exp $
|
-- $State: Exp $
|
--
|
--
|
-- Change History:
|
-- Change History:
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.4 2002/11/30 22:24:37 rherveille
|
|
-- Cleaned up code
|
|
--
|
-- Revision 1.3 2002/10/30 18:09:53 rherveille
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-- Revision 1.3 2002/10/30 18:09:53 rherveille
|
-- Fixed some reported minor start/stop generation timing issuess.
|
-- Fixed some reported minor start/stop generation timing issuess.
|
--
|
--
|
-- Revision 1.2 2002/06/15 07:37:04 rherveille
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-- Revision 1.2 2002/06/15 07:37:04 rherveille
|
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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| Line 66... |
Line 69... |
------------------------------------
|
------------------------------------
|
--
|
--
|
-- Translate simple commands into SCL/SDA transitions
|
-- Translate simple commands into SCL/SDA transitions
|
-- Each command has 5 states, A/B/C/D/idle
|
-- Each command has 5 states, A/B/C/D/idle
|
--
|
--
|
-- start: SCL ~~~~~~~~~~\____
|
-- start: SCL ~~~~~~~~~~~~~~\____
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-- SDA ~~~~~~~~\______
|
-- SDA XX/~~~~~~~\______
|
-- x | A | B | C | D | i
|
-- x | A | B | C | D | i
|
--
|
--
|
-- repstart SCL ____/~~~~\___
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-- repstart SCL ______/~~~~~~~\___
|
-- SDA __/~~~\______
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-- SDA __/~~~~~~~\______
|
-- x | A | B | C | D | i
|
-- x | A | B | C | D | i
|
--
|
--
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-- stop SCL ____/~~~~~~~~
|
-- stop SCL _______/~~~~~~~~~~~
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-- SDA ==\____/~~~~~
|
-- SDA ==\___________/~~~~~
|
-- x | A | B | C | D | i
|
-- x | A | B | C | D | i
|
--
|
--
|
--- write SCL ____/~~~~\____
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--- write SCL ______/~~~~~~~\____
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-- SDA ==X=========X=
|
-- SDA XXX===============XX
|
-- x | A | B | C | D | i
|
-- x | A | B | C | D | i
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--
|
--
|
--- read SCL ____/~~~~\____
|
--- read SCL ______/~~~~~~~\____
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-- SDA XXXX=====XXXX
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-- SDA XXXXXXX=XXXXXXXXXXX
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-- x | A | B | C | D | i
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-- x | A | B | C | D | i
|
--
|
--
|
|
|
-- Timing: Normal mode Fast mode
|
-- Timing: Normal mode Fast mode
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
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| Line 111... |
Line 114... |
ena : in std_logic; -- core enable signal
|
ena : in std_logic; -- core enable signal
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|
|
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
|
|
cmd : in std_logic_vector(3 downto 0);
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cmd : in std_logic_vector(3 downto 0);
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cmd_ack : out std_logic;
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cmd_ack : out std_logic; -- command completed
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busy : out std_logic;
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busy : out std_logic; -- i2c bus busy
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al : out std_logic; -- arbitration lost
|
|
|
din : in std_logic;
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din : in std_logic;
|
dout : out std_logic;
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dout : out std_logic;
|
|
|
-- i2c lines
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-- i2c lines
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| Line 139... |
Line 143... |
type states is (idle, start_a, start_b, start_c, start_d, start_e,
|
type states is (idle, start_a, start_b, start_c, start_d, start_e,
|
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
|
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
|
signal c_state : states;
|
signal c_state : states;
|
|
|
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
|
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
|
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
|
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
|
signal dscl_oen : std_logic; -- delayed scl_oen signals
|
signal dscl_oen : std_logic; -- delayed scl_oen signals
|
|
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
|
signal clk_en, slave_wait :std_logic; -- clock generation signals
|
signal clk_en, slave_wait :std_logic; -- clock generation signals
|
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
|
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
|
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
|
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
|
|
|
begin
|
begin
|
-- synchronize SCL and SDA inputs
|
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
|
synch_scl_sda: process(clk)
|
|
begin
|
|
if (clk'event and clk = '1') then
|
|
sSCL <= scl_i;
|
|
sSDA <= sda_i;
|
|
end if;
|
|
end process synch_SCL_SDA;
|
|
|
|
-- delay scl_oen
|
-- delay scl_oen
|
process (clk)
|
process (clk)
|
begin
|
begin
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
dscl_oen <= iscl_oen;
|
dscl_oen <= iscl_oen;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
|
|
slave_wait <= dscl_oen and not sSCL;
|
slave_wait <= dscl_oen and not sSCL;
|
|
|
-- generate clk enable signal
|
-- generate clk enable signal
|
gen_clken: process(clk, nReset)
|
gen_clken: process(clk, nReset)
|
begin
|
begin
|
| Line 179... |
Line 173... |
if (rst = '1') then
|
if (rst = '1') then
|
cnt <= (others => '0');
|
cnt <= (others => '0');
|
clk_en <= '1';
|
clk_en <= '1';
|
else
|
else
|
if ( (cnt = 0) or (ena = '0') ) then
|
if ( (cnt = 0) or (ena = '0') ) then
|
clk_en <= '1';
|
if (slave_wait = '0') then
|
cnt <= clk_cnt;
|
cnt <= clk_cnt;
|
|
clk_en <= '1';
|
|
else
|
|
cnt <= cnt;
|
|
clk_en <= '0';
|
|
end if;
|
else
|
else
|
if (slave_wait = '0') then
|
if (slave_wait = '0') then
|
cnt <= cnt -1;
|
cnt <= cnt -1;
|
end if;
|
end if;
|
clk_en <= '0';
|
clk_en <= '0';
|
| Line 194... |
Line 193... |
end process gen_clken;
|
end process gen_clken;
|
|
|
|
|
-- generate bus status controller
|
-- generate bus status controller
|
bus_status_ctrl: block
|
bus_status_ctrl: block
|
signal dSDA : std_logic;
|
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
|
signal sta_condition : std_logic;
|
signal sta_condition : std_logic; -- start detected
|
signal sto_condition : std_logic;
|
signal sto_condition : std_logic; -- stop detected
|
|
signal cmd_stop, dcmd_stop : std_logic; -- STOP command
|
signal ibusy : std_logic;
|
signal ibusy : std_logic; -- internal busy signal
|
|
begin
|
|
-- synchronize SCL and SDA inputs
|
|
synch_scl_sda: process(clk)
|
begin
|
begin
|
|
if (clk'event and clk = '1') then
|
|
sSCL <= scl_i;
|
|
sSDA <= sda_i;
|
|
|
|
dSCL <= sSCL;
|
|
dSDA <= sSDA;
|
|
end if;
|
|
end process synch_SCL_SDA;
|
|
|
-- detect start condition => detect falling edge on SDA while SCL is high
|
-- detect start condition => detect falling edge on SDA while SCL is high
|
-- detect stop condition => detect rising edge on SDA while SCL is high
|
-- detect stop condition => detect rising edge on SDA while SCL is high
|
detect_sta_sto: process(clk)
|
detect_sta_sto: process(clk)
|
begin
|
begin
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
dSDA <= sSDA; -- generate a delayed version of sSDA
|
|
|
|
sta_condition <= (not sSDA and dSDA) and sSCL;
|
sta_condition <= (not sSDA and dSDA) and sSCL;
|
sto_condition <= (sSDA and not dSDA) and sSCL;
|
sto_condition <= (sSDA and not dSDA) and sSCL;
|
end if;
|
end if;
|
end process detect_sta_sto;
|
end process detect_sta_sto;
|
|
|
-- generate bus busy signal
|
-- generate i2c-bus busy signal
|
gen_busy: process(clk, nReset)
|
gen_busy: process(clk, nReset)
|
begin
|
begin
|
if (nReset = '0') then
|
if (nReset = '0') then
|
ibusy <= '0';
|
ibusy <= '0';
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
| Line 225... |
Line 234... |
else
|
else
|
ibusy <= (sta_condition or ibusy) and not sto_condition;
|
ibusy <= (sta_condition or ibusy) and not sto_condition;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_busy;
|
end process gen_busy;
|
|
|
-- assign output
|
|
busy <= ibusy;
|
busy <= ibusy;
|
|
|
|
|
|
-- generate arbitration lost signal
|
|
gen_al: process(clk)
|
|
begin
|
|
if (clk'event and clk = '1') then
|
|
if (cmd = I2C_CMD_STOP) then
|
|
cmd_stop <= '1';
|
|
else
|
|
cmd_stop <= '0';
|
|
end if;
|
|
dcmd_stop <= cmd_stop;
|
|
|
|
al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
|
|
end if;
|
|
end process gen_al;
|
|
|
|
-- generate dout signal, store dout on rising edge of SCL
|
|
gen_dout: process(clk)
|
|
begin
|
|
if (clk'event and clk = '1') then
|
|
if (sSCL = '1' and dSCL = '0') then
|
|
dout <= sSDA;
|
|
end if;
|
|
end if;
|
|
end process gen_dout;
|
end block bus_status_ctrl;
|
end block bus_status_ctrl;
|
|
|
|
|
-- generate statemachine
|
-- generate statemachine
|
nxt_state_decoder : process (clk, nReset, c_state, cmd)
|
nxt_state_decoder : process (clk, nReset, c_state, cmd)
|
begin
|
begin
|
if (nReset = '0') then
|
if (nReset = '0') then
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '0';
|
cmd_ack <= '0';
|
dout <= '0';
|
|
iscl_oen <= '1';
|
iscl_oen <= '1';
|
isda_oen <= '1';
|
isda_oen <= '1';
|
|
sda_chk <= '0';
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (rst = '1') then
|
if (rst = '1') then
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '0';
|
cmd_ack <= '0';
|
dout <= '0';
|
|
iscl_oen <= '1';
|
iscl_oen <= '1';
|
isda_oen <= '1';
|
isda_oen <= '1';
|
|
sda_chk <= '0';
|
else
|
else
|
cmd_ack <= '0'; -- default no acknowledge
|
cmd_ack <= '0'; -- default no acknowledge
|
|
|
if (clk_en = '1') then
|
if (clk_en = '1') then
|
case (c_state) is
|
case (c_state) is
|
| Line 264... |
Line 297... |
when others => c_state <= idle; -- NOP command
|
when others => c_state <= idle; -- NOP command
|
end case;
|
end case;
|
|
|
iscl_oen <= iscl_oen; -- keep SCL in same state
|
iscl_oen <= iscl_oen; -- keep SCL in same state
|
isda_oen <= isda_oen; -- keep SDA in same state
|
isda_oen <= isda_oen; -- keep SDA in same state
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
-- start
|
-- start
|
when start_a =>
|
when start_a =>
|
c_state <= start_b;
|
c_state <= start_b;
|
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
|
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
|
isda_oen <= '1'; -- set SDA high
|
isda_oen <= '1'; -- set SDA high
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when start_b =>
|
when start_b =>
|
c_state <= start_c;
|
c_state <= start_c;
|
iscl_oen <= '1'; -- set SCL high
|
iscl_oen <= '1'; -- set SCL high
|
isda_oen <= '1'; -- keep SDA high
|
isda_oen <= '1'; -- keep SDA high
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when start_c =>
|
when start_c =>
|
c_state <= start_d;
|
c_state <= start_d;
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= '0'; -- set SDA low
|
isda_oen <= '0'; -- set SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when start_d =>
|
when start_d =>
|
c_state <= start_e;
|
c_state <= start_e;
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= '0'; -- keep SDA low
|
isda_oen <= '0'; -- keep SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when start_e =>
|
when start_e =>
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
iscl_oen <= '0'; -- set SCL low
|
iscl_oen <= '0'; -- set SCL low
|
isda_oen <= '0'; -- keep SDA low
|
isda_oen <= '0'; -- keep SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
-- stop
|
-- stop
|
when stop_a =>
|
when stop_a =>
|
c_state <= stop_b;
|
c_state <= stop_b;
|
iscl_oen <= '0'; -- keep SCL disabled
|
iscl_oen <= '0'; -- keep SCL low
|
isda_oen <= '0'; -- set SDA low
|
isda_oen <= '0'; -- set SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when stop_b =>
|
when stop_b =>
|
c_state <= stop_c;
|
c_state <= stop_c;
|
iscl_oen <= '1'; -- set SCL high
|
iscl_oen <= '1'; -- set SCL high
|
isda_oen <= '0'; -- keep SDA low
|
isda_oen <= '0'; -- keep SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when stop_c =>
|
when stop_c =>
|
c_state <= stop_d;
|
c_state <= stop_d;
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= '0'; -- keep SDA low
|
isda_oen <= '0'; -- keep SDA low
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when stop_d =>
|
when stop_d =>
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= '1'; -- set SDA high
|
isda_oen <= '1'; -- set SDA high
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
-- read
|
-- read
|
when rd_a =>
|
when rd_a =>
|
c_state <= rd_b;
|
c_state <= rd_b;
|
iscl_oen <= '0'; -- keep SCL low
|
iscl_oen <= '0'; -- keep SCL low
|
isda_oen <= '1'; -- tri-state SDA
|
isda_oen <= '1'; -- tri-state SDA
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when rd_b =>
|
when rd_b =>
|
c_state <= rd_c;
|
c_state <= rd_c;
|
iscl_oen <= '1'; -- set SCL high
|
iscl_oen <= '1'; -- set SCL high
|
isda_oen <= '1'; -- tri-state SDA
|
isda_oen <= '1'; -- tri-state SDA
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when rd_c =>
|
when rd_c =>
|
c_state <= rd_d;
|
c_state <= rd_d;
|
dout <= sSDA;
|
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= '1'; -- tri-state SDA
|
isda_oen <= '1'; -- tri-state SDA
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
when rd_d =>
|
when rd_d =>
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
iscl_oen <= '0'; -- set SCL low
|
iscl_oen <= '0'; -- set SCL low
|
isda_oen <= '1'; -- tri-state SDA
|
isda_oen <= '1'; -- tri-state SDA
|
|
sda_chk <= '0'; -- don't check SDA
|
|
|
-- write
|
-- write
|
when wr_a =>
|
when wr_a =>
|
c_state <= wr_b;
|
c_state <= wr_b;
|
iscl_oen <= '0'; -- keep SCL low
|
iscl_oen <= '0'; -- keep SCL low
|
isda_oen <= din; -- set SDA
|
isda_oen <= din; -- set SDA
|
|
sda_chk <= '0'; -- don't check SDA (SCL low)
|
|
|
when wr_b =>
|
when wr_b =>
|
c_state <= wr_c;
|
c_state <= wr_c;
|
iscl_oen <= '1'; -- set SCL high
|
iscl_oen <= '1'; -- set SCL high
|
isda_oen <= din; -- keep SDA
|
isda_oen <= din; -- keep SDA
|
|
sda_chk <= '1'; -- check SDA
|
|
|
when wr_c =>
|
when wr_c =>
|
c_state <= wr_d;
|
c_state <= wr_d;
|
iscl_oen <= '1'; -- keep SCL high
|
iscl_oen <= '1'; -- keep SCL high
|
isda_oen <= din; -- keep SDA
|
isda_oen <= din; -- keep SDA
|
|
sda_chk <= '1'; -- check SDA
|
|
|
when wr_d =>
|
when wr_d =>
|
c_state <= idle;
|
c_state <= idle;
|
cmd_ack <= '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
iscl_oen <= '0'; -- set SCL low
|
iscl_oen <= '0'; -- set SCL low
|
isda_oen <= din; -- keep SDA
|
isda_oen <= din; -- keep SDA
|
|
sda_chk <= '0'; -- don't check SDA (SCL low)
|
|
|
when others =>
|
when others =>
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
