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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 31 and 34

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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.5 2002-12-26 16:05:47 rherveille Exp $
--  $Id: i2c_master_bit_ctrl.vhd,v 1.6 2003-02-01 02:03:06 rherveille Exp $
--
--
--  $Date: 2002-12-26 16:05:47 $
--  $Date: 2003-02-01 02:03:06 $
--  $Revision: 1.5 $
--  $Revision: 1.6 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.5  2002/12/26 16:05:47  rherveille
 
--               Core is now a Multimaster I2C controller.
 
--
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--               Cleaned up code
--
--
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Fixed some reported minor start/stop generation timing issuess.
--               Fixed some reported minor start/stop generation timing issuess.
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        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal clk_en, slave_wait :std_logic;           -- clock generation signals
        signal clk_en, slave_wait :std_logic;           -- clock generation signals
 
        signal ial                : std_logic;          -- internal arbitration lost signal
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
 
 
begin
begin
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
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                dcmd_stop <= cmd_stop;
                dcmd_stop <= cmd_stop;
 
 
                al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
                al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
              end if;
              end if;
            end process gen_al;
            end process gen_al;
 
            ial <= al;
 
 
            -- generate dout signal, store dout on rising edge of SCL
            -- generate dout signal, store dout on rising edge of SCL
            gen_dout: process(clk)
            gen_dout: process(clk)
            begin
            begin
              if (clk'event and clk = '1') then
              if (clk'event and clk = '1') then
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              cmd_ack  <= '0';
              cmd_ack  <= '0';
              iscl_oen <= '1';
              iscl_oen <= '1';
              isda_oen <= '1';
              isda_oen <= '1';
              sda_chk  <= '0';
              sda_chk  <= '0';
            elsif (clk'event and clk = '1') then
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
              if (rst = '1' or ial = '1') then
                c_state  <= idle;
                c_state  <= idle;
                cmd_ack  <= '0';
                cmd_ack  <= '0';
                iscl_oen <= '1';
                iscl_oen <= '1';
                isda_oen <= '1';
                isda_oen <= '1';
                sda_chk  <= '0';
                sda_chk  <= '0';
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        scl_oen <= iscl_oen;
        scl_oen <= iscl_oen;
        sda_o   <= '0';
        sda_o   <= '0';
        sda_oen <= isda_oen;
        sda_oen <= isda_oen;
end architecture structural;
end architecture structural;
 
 
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