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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.12 2004-05-07 11:53:31 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.13 2006-10-06 10:48:24 rherveille Exp $
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--
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--
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-- $Date: 2004-05-07 11:53:31 $
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-- $Date: 2006-10-06 10:48:24 $
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-- $Revision: 1.12 $
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-- $Revision: 1.13 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.12 2004/05/07 11:53:31 rherveille
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-- Fixed previous fix :) Made a variable vs signal mistake.
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--
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-- Revision 1.11 2004/05/07 11:04:00 rherveille
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-- Revision 1.11 2004/05/07 11:04:00 rherveille
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-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
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-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
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--
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--
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-- Revision 1.10 2004/02/27 07:49:43 rherveille
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-- Revision 1.10 2004/02/27 07:49:43 rherveille
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-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
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-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
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Line 194... |
Line 197... |
clk_en <= '1';
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clk_en <= '1';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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cnt <= (others => '0');
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cnt <= (others => '0');
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clk_en <= '1';
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clk_en <= '1';
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else
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elsif ( (cnt = 0) or (ena = '0') ) then
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if ( (cnt = 0) or (ena = '0') ) then
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if (slave_wait = '0') then
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cnt <= clk_cnt;
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cnt <= clk_cnt;
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clk_en <= '1';
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clk_en <= '1';
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else
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elsif (slave_wait = '1') then
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cnt <= cnt;
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cnt <= cnt;
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clk_en <= '0';
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clk_en <= '0';
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end if;
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else
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else
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if (slave_wait = '0') then
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cnt <= cnt -1;
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cnt <= cnt -1;
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end if;
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clk_en <= '0';
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clk_en <= '0';
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end if;
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end if
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end if;
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end if
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end if;
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end process gen_clken;
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end process gen_clken;
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-- generate bus status controller
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-- generate bus status controller
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bus_status_ctrl: block
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bus_status_ctrl: block
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