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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 53 and 59

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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.12 2004-05-07 11:53:31 rherveille Exp $
--  $Id: i2c_master_bit_ctrl.vhd,v 1.13 2006-10-06 10:48:24 rherveille Exp $
--
--
--  $Date: 2004-05-07 11:53:31 $
--  $Date: 2006-10-06 10:48:24 $
--  $Revision: 1.12 $
--  $Revision: 1.13 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.12  2004/05/07 11:53:31  rherveille
 
--               Fixed previous fix :) Made a variable vs signal mistake.
 
--
--               Revision 1.11  2004/05/07 11:04:00  rherveille
--               Revision 1.11  2004/05/07 11:04:00  rherveille
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
--
--               Revision 1.10  2004/02/27 07:49:43  rherveille
--               Revision 1.10  2004/02/27 07:49:43  rherveille
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
Line 194... Line 197...
              clk_en <= '1';
              clk_en <= '1';
            elsif (clk'event and clk = '1') then
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
              if (rst = '1') then
                cnt    <= (others => '0');
                cnt    <= (others => '0');
                clk_en <= '1';
                clk_en <= '1';
              else
              elsif ( (cnt = 0) or (ena = '0') ) then
                if ( (cnt = 0) or (ena = '0') ) then
 
                  if (slave_wait = '0') then
 
                    cnt    <= clk_cnt;
                    cnt    <= clk_cnt;
                    clk_en <= '1';
                    clk_en <= '1';
                  else
              elsif (slave_wait = '1') then
                    cnt    <= cnt;
                    cnt    <= cnt;
                    clk_en <= '0';
                    clk_en <= '0';
                  end if;
 
                else
                else
                  if (slave_wait = '0') then
 
                    cnt <= cnt -1;
                    cnt <= cnt -1;
                  end if;
 
                  clk_en <= '0';
                  clk_en <= '0';
                end if;
              end if
              end if;
            end if
            end if;
 
        end process gen_clken;
        end process gen_clken;
 
 
 
 
        -- generate bus status controller
        -- generate bus status controller
        bus_status_ctrl: block
        bus_status_ctrl: block

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