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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 64 and 66

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Rev 64 Rev 66
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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.15 2009-01-20 10:34:51 rherveille Exp $
--  $Id: i2c_master_bit_ctrl.vhd,v 1.16 2009-01-20 20:40:36 rherveille Exp $
--
--
--  $Date: 2009-01-20 10:34:51 $
--  $Date: 2009-01-20 20:40:36 $
--  $Revision: 1.15 $
--  $Revision: 1.16 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.15  2009/01/20 10:34:51  rherveille
 
--               Added SCL clock synchronization logic
 
--               Fixed slave_wait signal generation
 
--
--               Revision 1.14  2006/10/11 12:10:13  rherveille
--               Revision 1.14  2006/10/11 12:10:13  rherveille
--               Added missing semicolons ';' on endif
--               Added missing semicolons ';' on endif
--
--
--               Revision 1.13  2006/10/06 10:48:24  rherveille
--               Revision 1.13  2006/10/06 10:48:24  rherveille
--               fixed short scl high pulse after clock stretch
--               fixed short scl high pulse after clock stretch
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        process (clk, nReset)
        process (clk, nReset)
        begin
        begin
            if (nReset = '0') then
            if (nReset = '0') then
              slave_wait <= '0';
              slave_wait <= '0';
            else
            else
              slave_wait <= (scl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
              slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
            end if;
            end if;
        end process;
        end process;
 
 
        -- master drives SCL high, but another master pulls it low
        -- master drives SCL high, but another master pulls it low
        -- master start counting down its low cycle now (clock synchronization)
        -- master start counting down its low cycle now (clock synchronization)
        scl_sync <= dSCL and not sSCL and scl_oen;
        scl_sync <= dSCL and not sSCL and iscl_oen;
 
 
        -- generate clk enable signal
        -- generate clk enable signal
        gen_clken: process(clk, nReset)
        gen_clken: process(clk, nReset)
        begin
        begin
            if (nReset = '0') then
            if (nReset = '0') then

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