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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 66 and 67
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| Rev 66 |
Rev 67 |
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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.16 2009-01-20 20:40:36 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
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--
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--
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-- $Date: 2009-01-20 20:40:36 $
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-- $Date: 2009-02-04 20:17:34 $
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-- $Revision: 1.16 $
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-- $Revision: 1.17 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.16 2009/01/20 20:40:36 rherveille
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-- Fixed type iscl_oen instead of scl_oen
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--
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-- Revision 1.15 2009/01/20 10:34:51 rherveille
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-- Revision 1.15 2009/01/20 10:34:51 rherveille
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-- Added SCL clock synchronization logic
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-- Added SCL clock synchronization logic
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-- Fixed slave_wait signal generation
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-- Fixed slave_wait signal generation
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--
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--
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-- Revision 1.14 2006/10/11 12:10:13 rherveille
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-- Revision 1.14 2006/10/11 12:10:13 rherveille
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-- slave_wait remains asserted until the slave (other master) releases SCL
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-- slave_wait remains asserted until the slave (other master) releases SCL
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process (clk, nReset)
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process (clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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slave_wait <= '0';
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slave_wait <= '0';
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else
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elsif (clk'event and clk = '1') then
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slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
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slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
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end if;
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end if;
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end process;
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end process;
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-- master drives SCL high, but another master pulls it low
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-- master drives SCL high, but another master pulls it low
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