| Line 140... |
Line 140... |
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity i2c_master_bit_ctrl is
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entity i2c_master_bit_ctrl is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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| Line 188... |
Line 188... |
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
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signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
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signal clk_en : std_logic; -- statemachine clock enable
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signal clk_en : std_logic; -- statemachine clock enable
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signal scl_sync, slave_wait : std_logic; -- clock generation signals
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signal scl_sync, slave_wait : std_logic; -- clock generation signals
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signal ial : std_logic; -- internal arbitration lost signal
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signal ial : std_logic; -- internal arbitration lost signal
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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begin
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begin
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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-- delay scl_oen
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-- delay scl_oen
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process (clk)
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process (clk, nReset)
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begin
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begin
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if (clk'event and clk = '1') then
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if (nReset = '0') then
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dscl_oen <= '0';
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elsif (clk'event and clk = '1') then
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dscl_oen <= iscl_oen;
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dscl_oen <= iscl_oen;
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end if;
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end if;
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end process;
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end process;
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-- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
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-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
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-- slave_wait remains asserted until the slave (other master) releases SCL
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-- slave_wait remains asserted until the slave releases SCL
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process (clk, nReset)
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process (clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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slave_wait <= '0';
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slave_wait <= '0';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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| Line 223... |
Line 224... |
begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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cnt <= (others => '0');
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cnt <= (others => '0');
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clk_en <= '1';
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clk_en <= '1';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
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cnt <= (others => '0');
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clk_en <= '1';
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elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then
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cnt <= clk_cnt;
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cnt <= clk_cnt;
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clk_en <= '1';
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clk_en <= '1';
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elsif (slave_wait = '1') then
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elsif (slave_wait = '1') then
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cnt <= cnt;
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cnt <= cnt;
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clk_en <= '0';
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clk_en <= '0';
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| Line 242... |
Line 240... |
end process gen_clken;
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end process gen_clken;
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-- generate bus status controller
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-- generate bus status controller
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bus_status_ctrl: block
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bus_status_ctrl: block
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signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
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signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
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signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
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signal sta_condition : std_logic; -- start detected
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signal sta_condition : std_logic; -- start detected
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signal sto_condition : std_logic; -- stop detected
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signal sto_condition : std_logic; -- stop detected
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signal cmd_stop : std_logic; -- STOP command
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signal cmd_stop : std_logic; -- STOP command
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signal ibusy : std_logic; -- internal busy signal
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signal ibusy : std_logic; -- internal busy signal
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begin
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begin
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-- synchronize SCL and SDA inputs
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-- capture SCL and SDA
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synch_scl_sda: process(clk, nReset)
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capture_scl_sda: process(clk, nReset)
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begin
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if (nReset = '0') then
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cSCL <= "00";
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cSDA <= "00";
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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cSCL <= "00";
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cSDA <= "00";
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else
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cSCL <= (cSCL(0) & scl_i);
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cSDA <= (cSDA(0) & sda_i);
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end if;
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end if;
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end process capture_scl_sda;
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-- filter SCL and SDA; (attempt to) remove glitches
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filter_divider: process(clk, nReset)
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begin
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if (nReset = '0') then
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filter_cnt <= (others => '0');
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elsif (clk'event and clk = '1') then
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if ((rst = '1') or (filter_cnt = 0)) then
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filter_cnt <= clk_cnt(15 downto 2);
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else
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filter_cnt <= filter_cnt -1;
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end if;
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end if;
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end process filter_divider;
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filter_scl_sda: process(clk, nReset)
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begin
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if (nReset = '0') then
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fSCL <= (others => '1');
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fSDA <= (others => '1');
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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fSCL <= (others => '1');
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fSDA <= (others => '1');
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elsif (filter_cnt = 0) then
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fSCL <= (fSCL(1 downto 0) & cSCL(1));
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fSDA <= (fSDA(1 downto 0) & cSDA(1));
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end if;
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end if;
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end process filter_scl_sda;
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-- generate filtered SCL and SDA signals
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scl_sda: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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sSCL <= '1';
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sSCL <= '1';
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sSDA <= '1';
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sSDA <= '1';
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| Line 264... |
Line 312... |
sSDA <= '1';
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sSDA <= '1';
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dSCL <= '1';
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dSCL <= '1';
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dSDA <= '1';
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dSDA <= '1';
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else
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else
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sSCL <= scl_i;
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sSCL <= (fSCL(2) and fSCL(1)) or
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sSDA <= sda_i;
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(fSCL(2) and fSCL(0)) or
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(fSCL(1) and fSCL(0));
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sSDA <= (fSDA(2) and fSDA(1)) or
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(fSDA(2) and fSDA(0)) or
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(fSCL(1) and fSCL(0));
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dSCL <= sSCL;
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dSCL <= sSCL;
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dSDA <= sSDA;
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dSDA <= sSDA;
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end if;
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end if;
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end if;
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end if;
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end process synch_SCL_SDA;
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end process scl_sda;
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-- detect start condition => detect falling edge on SDA while SCL is high
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-- detect start condition => detect falling edge on SDA while SCL is high
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-- detect stop condition => detect rising edge on SDA while SCL is high
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-- detect stop condition => detect rising edge on SDA while SCL is high
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detect_sta_sto: process(clk, nReset)
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detect_sta_sto: process(clk, nReset)
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begin
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begin
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| Line 291... |
Line 344... |
sto_condition <= (sSDA and not dSDA) and sSCL;
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sto_condition <= (sSDA and not dSDA) and sSCL;
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end if;
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end if;
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end if;
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end if;
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end process detect_sta_sto;
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end process detect_sta_sto;
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-- generate i2c-bus busy signal
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-- generate i2c-bus busy signal
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gen_busy: process(clk, nReset)
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gen_busy: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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ibusy <= '0';
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ibusy <= '0';
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| Line 330... |
Line 384... |
cmd_stop <= '0';
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cmd_stop <= '0';
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end if;
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end if;
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end if;
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end if;
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if (c_state = idle) then
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if (c_state = idle) then
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ial <= (sda_chk and not sSDA and isda_oen);
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else
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ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
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ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
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else
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ial <= (sda_chk and not sSDA and isda_oen);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process gen_al;
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end process gen_al;
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al <= ial;
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al <= ial;
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-- generate dout signal, store dout on rising edge of SCL
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-- generate dout signal, store dout on rising edge of SCL
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gen_dout: process(clk)
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gen_dout: process(clk, nReset)
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begin
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begin
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if (clk'event and clk = '1') then
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if (nReset = '0') then
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dout <= '0';
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elsif (clk'event and clk = '1') then
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if (sSCL = '1' and dSCL = '0') then
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if (sSCL = '1' and dSCL = '0') then
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dout <= sSDA;
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dout <= sSDA;
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end if;
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end if;
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end if;
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end if;
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end process gen_dout;
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end process gen_dout;
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end block bus_status_ctrl;
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end block bus_status_ctrl;
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-- generate statemachine
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-- generate statemachine
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nxt_state_decoder : process (clk, nReset, c_state, cmd)
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nxt_state_decoder : process (clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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c_state <= idle;
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c_state <= idle;
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cmd_ack <= '0';
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cmd_ack <= '0';
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iscl_oen <= '1';
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iscl_oen <= '1';
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| Line 482... |
Line 538... |
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when wr_b =>
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when wr_b =>
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c_state <= wr_c;
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c_state <= wr_c;
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iscl_oen <= '1'; -- set SCL high
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iscl_oen <= '1'; -- set SCL high
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isda_oen <= din; -- keep SDA
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isda_oen <= din; -- keep SDA
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sda_chk <= '1'; -- check SDA
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sda_chk <= '0'; -- don't check SDA yet
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-- Allow some more time for SDA and SCL to settle
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when wr_c =>
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when wr_c =>
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c_state <= wr_d;
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c_state <= wr_d;
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iscl_oen <= '1'; -- keep SCL high
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iscl_oen <= '1'; -- keep SCL high
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isda_oen <= din; -- keep SDA
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isda_oen <= din; -- keep SDA
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