| Line 35... |
Line 35... |
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
-- CVS Log
|
-- CVS Log
|
--
|
--
|
-- $Id: i2c_master_byte_ctrl.vhd,v 1.2 2002-11-30 22:24:37 rherveille Exp $
|
-- $Id: i2c_master_byte_ctrl.vhd,v 1.3 2002-12-26 16:05:47 rherveille Exp $
|
--
|
--
|
-- $Date: 2002-11-30 22:24:37 $
|
-- $Date: 2002-12-26 16:05:47 $
|
-- $Revision: 1.2 $
|
-- $Revision: 1.3 $
|
-- $Author: rherveille $
|
-- $Author: rherveille $
|
-- $Locker: $
|
-- $Locker: $
|
-- $State: Exp $
|
-- $State: Exp $
|
--
|
--
|
-- Change History:
|
-- Change History:
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2002/11/30 22:24:37 rherveille
|
|
-- Cleaned up code
|
|
--
|
-- Revision 1.1 2001/11/05 12:02:33 rherveille
|
-- Revision 1.1 2001/11/05 12:02:33 rherveille
|
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
|
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
|
-- Code updated, is now up-to-date to doc. rev.0.4.
|
-- Code updated, is now up-to-date to doc. rev.0.4.
|
-- Added headers.
|
-- Added headers.
|
--
|
--
|
| Line 81... |
Line 84... |
write,
|
write,
|
ack_in : std_logic;
|
ack_in : std_logic;
|
din : in std_logic_vector(7 downto 0);
|
din : in std_logic_vector(7 downto 0);
|
|
|
-- output signals
|
-- output signals
|
cmd_ack : out std_logic;
|
cmd_ack : out std_logic; -- command done
|
ack_out : out std_logic;
|
ack_out : out std_logic;
|
i2c_busy : out std_logic;
|
i2c_busy : out std_logic; -- arbitration lost
|
|
i2c_al : out std_logic; -- i2c bus busy
|
dout : out std_logic_vector(7 downto 0);
|
dout : out std_logic_vector(7 downto 0);
|
|
|
-- i2c lines
|
-- i2c lines
|
scl_i : in std_logic; -- i2c clock line input
|
scl_i : in std_logic; -- i2c clock line input
|
scl_o : out std_logic; -- i2c clock line output
|
scl_o : out std_logic; -- i2c clock line output
|
| Line 107... |
Line 111... |
ena : in std_logic; -- core enable signal
|
ena : in std_logic; -- core enable signal
|
|
|
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
|
|
|
cmd : in std_logic_vector(3 downto 0);
|
cmd : in std_logic_vector(3 downto 0);
|
cmd_ack : out std_logic;
|
cmd_ack : out std_logic; -- command done
|
busy : out std_logic;
|
busy : out std_logic; -- i2c bus busy
|
|
al : out std_logic; -- arbitration lost
|
|
|
din : in std_logic;
|
din : in std_logic;
|
dout : out std_logic;
|
dout : out std_logic;
|
|
|
-- i2c lines
|
-- i2c lines
|
| Line 133... |
Line 138... |
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
|
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
|
|
|
-- signals for bit_controller
|
-- signals for bit_controller
|
signal core_cmd : std_logic_vector(3 downto 0);
|
signal core_cmd : std_logic_vector(3 downto 0);
|
signal core_ack, core_txd, core_rxd : std_logic;
|
signal core_ack, core_txd, core_rxd : std_logic;
|
|
signal al : std_logic;
|
|
|
-- signals for shift register
|
-- signals for shift register
|
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
|
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
|
signal shift, ld : std_logic;
|
signal shift, ld : std_logic;
|
|
|
| Line 145... |
Line 151... |
signal dcnt : unsigned(2 downto 0); -- data counter
|
signal dcnt : unsigned(2 downto 0); -- data counter
|
signal cnt_done : std_logic;
|
signal cnt_done : std_logic;
|
|
|
begin
|
begin
|
-- hookup bit_controller
|
-- hookup bit_controller
|
u1: i2c_master_bit_ctrl port map(
|
bit_ctrl: i2c_master_bit_ctrl port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
nReset => nReset,
|
nReset => nReset,
|
ena => ena,
|
ena => ena,
|
clk_cnt => clk_cnt,
|
clk_cnt => clk_cnt,
|
cmd => core_cmd,
|
cmd => core_cmd,
|
cmd_ack => core_ack,
|
cmd_ack => core_ack,
|
busy => i2c_busy,
|
busy => i2c_busy,
|
|
al => al,
|
din => core_txd,
|
din => core_txd,
|
dout => core_rxd,
|
dout => core_rxd,
|
scl_i => scl_i,
|
scl_i => scl_i,
|
scl_o => scl_o,
|
scl_o => scl_o,
|
scl_oen => scl_oen,
|
scl_oen => scl_oen,
|
sda_i => sda_i,
|
sda_i => sda_i,
|
sda_o => sda_o,
|
sda_o => sda_o,
|
sda_oen => sda_oen
|
sda_oen => sda_oen
|
);
|
);
|
|
i2c_al <= al;
|
|
|
-- generate host-command-acknowledge
|
-- generate host-command-acknowledge
|
cmd_ack <= host_ack;
|
cmd_ack <= host_ack;
|
|
|
-- generate go-signal
|
-- generate go-signal
|
| Line 228... |
Line 236... |
ld <= '0';
|
ld <= '0';
|
host_ack <= '0';
|
host_ack <= '0';
|
c_state <= st_idle;
|
c_state <= st_idle;
|
ack_out <= '0';
|
ack_out <= '0';
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (rst = '1') then
|
if (rst = '1' or al = '1') then
|
core_cmd <= I2C_CMD_NOP;
|
core_cmd <= I2C_CMD_NOP;
|
core_txd <= '0';
|
core_txd <= '0';
|
shift <= '0';
|
shift <= '0';
|
ld <= '0';
|
ld <= '0';
|
host_ack <= '0';
|
host_ack <= '0';
|
