| Line 44... |
Line 44... |
output all_restarts, use_d_for_i, turn_on_single_intlk, turn_on_op_intlk,
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output all_restarts, use_d_for_i, turn_on_single_intlk, turn_on_op_intlk,
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output stop_code, code_69, tlu_sig,
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output stop_code, code_69, tlu_sig,
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output mult_sig, divide_sig, reset_sig, no_reset_sig, abs_sig, no_abs_sig,
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output mult_sig, divide_sig, reset_sig, no_reset_sig, abs_sig, no_abs_sig,
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output lower_sig, upper_sig, add_sig, subt_sig,
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output lower_sig, upper_sig, add_sig, subt_sig,
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output right_shift_sig, left_shift_sig, half_correct_sig, shift_count_sig,
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output right_shift_sig, left_shift_sig, half_correct_sig, shift_count_sig,
|
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output end_shift_control,
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output reg overflow_sense_latch
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output reg overflow_sense_latch
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);
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);
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Miscellaneous signals
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// Miscellaneous signals
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| Line 96... |
Line 97... |
// 31 -- Shift and Round
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// 31 -- Shift and Round
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// 35 -- Shift Left
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// 35 -- Shift Left
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// 36 -- Shift Left and Count
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// 36 -- Shift Left and Count
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg shift_control_latch;
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reg shift_control_latch;
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wire end_shift_control;
|
|
digit_pulse end_shift (rst, cp, ~shift_control_latch, 1'b1, end_shift_control);
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digit_pulse end_shift (rst, cp, ~shift_control_latch, 1'b1, end_shift_control);
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wire shift_control_on_p = d_control & d10u & ~single_intlk & opreg_t[`biq_b0]
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wire shift_control_on_p = d_control & d10u & ~single_intlk & opreg_t[`biq_b0]
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& opreg_t[`biq_q3];
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& opreg_t[`biq_q3];
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always @(posedge ap)
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always @(posedge ap)
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if (rst) begin
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if (rst) begin
|
