| Line 29... |
Line 29... |
// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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`include "defines.v"
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|
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module operator_ctl (
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module operator_ctl (
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input rst,
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input rst, clk,
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input ap, dp,
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input ap, dp,
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input dx, d0, d1, d2, d3, d4, d5, d6, d10,
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input dx, d0, d1, d2, d3, d4, d5, d6, d10,
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input wu, hp,
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input wu, hp,
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input [0:3] early_idx, ontime_idx,
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input [0:3] early_idx, ontime_idx,
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input [0:6] cmd_digit_in, io_buffer_in,
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input [0:6] cmd_digit_in, io_buffer_in, gs_in,
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input [0:5] command,
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input [0:5] command,
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output reg[0:6] data_out, addr_out,
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output reg[0:6] data_out, addr_out, console_out,
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output reg console_to_addr,
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output reg console_to_addr,
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output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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storage_control,
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storage_control,
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output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
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output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
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hard_reset,
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output reg[0:6] cmd_digit_out,
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output reg[0:6] cmd_digit_out,
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output reg busy, digit_ready,
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output reg busy, digit_ready,
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output reg punch_card, read_card, card_digit_ready
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output reg punch_card, read_card, card_digit_ready
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);
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);
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| Line 70... |
Line 71... |
assign ri_storage = disp_sw_ri;
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assign ri_storage = disp_sw_ri;
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assign ro_storage = disp_sw_ro;
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assign ro_storage = disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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do_pgm_reset, do_acc_reset;
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do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
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reg [0:5] state;
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reg [0:5] state;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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wire [0:14] gs_band_addr;
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wire [0:14] gs_band_addr;
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wire [0:9] gs_word_offset;
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wire [0:9] gs_word_offset;
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| Line 92... |
Line 93... |
`define state_acc_reset_2 6'd6
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`define state_acc_reset_2 6'd6
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`define state_err_reset_1 6'd7
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`define state_err_reset_1 6'd7
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`define state_err_reset_2 6'd8
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`define state_err_reset_2 6'd8
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`define state_err_sense_reset_1 6'd9
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`define state_err_sense_reset_1 6'd9
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`define state_err_sense_reset_2 6'd10
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`define state_err_sense_reset_2 6'd10
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`define state_hard_reset_1 6'd11
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|
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`define state_storage_entry_sw_1 6'd11
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`define state_storage_entry_sw_1 6'd12
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`define state_storage_entry_sw_2 6'd12
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`define state_storage_entry_sw_2 6'd13
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`define state_addr_sel_sw_1 6'd13
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`define state_addr_sel_sw_1 6'd14
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`define state_addr_sel_sw_2 6'd14
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`define state_addr_sel_sw_2 6'd15
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|
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`define state_xfer_key_1 6'd15
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`define state_xfer_key_1 6'd16
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`define state_xfer_key_2 6'd16
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`define state_xfer_key_2 6'd17
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`define state_pgm_start_key_1 6'd17
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`define state_pgm_start_key_1 6'd18
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`define state_pgm_start_key_2 6'd18
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`define state_pgm_start_key_2 6'd19
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`define state_pgm_stop_key_1 6'd19
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`define state_pgm_stop_key_1 6'd20
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`define state_pgm_stop_key_2 6'd20
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`define state_pgm_stop_key_2 6'd21
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|
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`define state_read_gs_1 6'd31
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`define state_read_gs_1 6'd30
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`define state_read_gs_2 6'd32
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`define state_read_gs_2 6'd31
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`define state_read_gs_3 6'd33
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`define state_read_gs_3 6'd32
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`define state_read_gs_4 6'd34
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`define state_read_gs_4 6'd33
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`define state_read_gs_5 6'd35
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`define state_read_gs_5 6'd34
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`define state_clear_drum_1 6'd50
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`define state_clear_drum_2 6'd51
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`define state_clear_drum_3 6'd52
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Operator console state machine
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// Operator console state machine
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge dp) begin
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always @(posedge clk) begin
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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pgm_stop <= 0;
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pgm_stop <= 0;
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err_reset <= 0;
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err_reset <= 0;
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err_sense_reset <= 0;
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err_sense_reset <= 0;
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man_pgm_reset <= 0;
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man_pgm_reset <= 0;
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man_acc_reset <= 0;
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man_acc_reset <= 0;
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set_8000 <= 0;
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set_8000 <= 0;
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reset_8000 <= 0;
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reset_8000 <= 0;
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hard_reset <= 0;
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// reset console switches
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// reset console switches
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pgm_sw_stop <= 0;
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pgm_sw_stop <= 0;
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pgm_sw_run <= 1;
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pgm_sw_run <= 1;
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half_cycle_sw_run <= 1;
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half_cycle_sw_half <= 0;
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ctl_sw_addr_stop <= 0;
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ctl_sw_addr_stop <= 0;
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ctl_sw_run <= 1;
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ctl_sw_run <= 1;
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ctl_sw_manual <= 0;
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ctl_sw_manual <= 0;
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disp_sw_lacc <= 0;
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disp_sw_lacc <= 0;
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disp_sw_uacc <= 0;
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disp_sw_uacc <= 0;
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| Line 154... |
Line 163... |
do_reset_console <= 0;
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do_reset_console <= 0;
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do_err_reset <= 0;
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do_err_reset <= 0;
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do_err_sense_reset <= 0;
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do_err_sense_reset <= 0;
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do_pgm_reset <= 0;
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do_pgm_reset <= 0;
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do_acc_reset <= 0;
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do_acc_reset <= 0;
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do_hard_reset <= 0;
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do_clear_drum <= 0;
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gs_ram_addr <= 15'd0;
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gs_ram_addr <= 15'd0;
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read_gs <= 0;
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read_gs <= 0;
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write_gs <= 0;
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write_gs <= 0;
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end else begin
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console_out <= `biq_blank;
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end else if (dp) begin
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case (state)
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case (state)
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`state_idle: begin
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`state_idle: begin
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case (command)
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case (command)
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`cmd_none: begin
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`cmd_none: begin
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if (do_power_on_reset) begin
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if (do_power_on_reset) begin
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| Line 170... |
Line 182... |
do_reset_console <= 1;
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do_reset_console <= 1;
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do_pgm_reset <= 1;
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do_pgm_reset <= 1;
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do_acc_reset <= 1;
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do_acc_reset <= 1;
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do_err_reset <= 1;
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do_err_reset <= 1;
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do_err_sense_reset <= 1;
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do_err_sense_reset <= 1;
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do_hard_reset <= 1;
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do_clear_drum <= 1;
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end else if (do_hard_reset) begin
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do_hard_reset <= 0;
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hard_reset <= 1;
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state <= `state_hard_reset_1;
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end else if (do_reset_console) begin
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end else if (do_reset_console) begin
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do_reset_console <= 0;
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do_reset_console <= 0;
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state <= `state_reset_console_1;
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state <= `state_reset_console_1;
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end else if (do_clear_drum) begin
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do_clear_drum <= 0;
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gs_ram_addr <= 15'd0;
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state <= `state_clear_drum_1;
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end else if (do_pgm_reset) begin
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end else if (do_pgm_reset) begin
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do_pgm_reset <= 0;
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do_pgm_reset <= 0;
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state <= `state_pgm_reset_1;
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state <= `state_pgm_reset_1;
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end else if (do_acc_reset) begin
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end else if (do_acc_reset) begin
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do_acc_reset <= 0;
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do_acc_reset <= 0;
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| Line 352... |
Line 374... |
pgm_stop <= 1;
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pgm_stop <= 1;
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state <= `state_pgm_stop_key_1;
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state <= `state_pgm_stop_key_1;
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end
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end
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`cmd_pgm_reset_key: begin
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`cmd_pgm_reset_key: begin
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busy <= 1;
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do_pgm_reset <= 1;
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do_pgm_reset <= 1;
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do_err_reset <= 1;
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do_err_reset <= 1;
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end
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end
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`cmd_comp_reset_key: begin
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`cmd_comp_reset_key: begin
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busy <= 1;
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do_pgm_reset <= 1;
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do_pgm_reset <= 1;
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do_acc_reset <= 1;
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do_acc_reset <= 1;
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do_err_reset <= 1;
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do_err_reset <= 1;
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end
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end
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`cmd_acc_reset_key: begin
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`cmd_acc_reset_key: begin
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busy <= 1;
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do_acc_reset <= 1;
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do_acc_reset <= 1;
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do_err_reset <= 1;
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do_err_reset <= 1;
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end
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end
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`cmd_err_reset_key: begin
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`cmd_err_reset_key: begin
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busy <= 1;
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do_err_reset <= 1;
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do_err_reset <= 1;
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end
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end
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`cmd_err_sense_reset_key: begin
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`cmd_err_sense_reset_key: begin
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busy <= 1;
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do_err_sense_reset <= 1;
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do_err_sense_reset <= 1;
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end
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end
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Read from general storage:
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// Read from general storage:
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| Line 419... |
Line 446... |
// dx: blank
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// dx: blank
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// d0: minus
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// d0: minus
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// d1-d10: zero
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// d1-d10: zero
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// gs_ram_addr++
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// gs_ram_addr++
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`cmd_clear_gs: begin
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`cmd_clear_gs: begin
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if (ctl_sw_manual) begin
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busy <= 1;
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do_clear_drum <= 1;
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end
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end
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end
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`cmd_load_gs: begin
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`cmd_load_gs: begin
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end
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end
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| Line 434... |
Line 464... |
end
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end
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`cmd_reset_console: begin
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`cmd_reset_console: begin
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end
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end
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`cmd_hard_reset: begin
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busy <= 1;
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do_hard_reset <= 1;
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end
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endcase;
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endcase;
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end
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end
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// Reset console
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// Reset console
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`state_reset_console_1: begin
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`state_reset_console_1: begin
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if (d10) state <= `state_reset_console_2;
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if (d10) state <= `state_reset_console_2;
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end
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end
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`state_reset_console_2: begin
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`state_reset_console_2: begin
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storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
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storage_entry_sw[ontime_idx] <= dx? `biq_blank
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: d0? `biq_plus : `biq_0;
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addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
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addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
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if (d10) state <= `state_idle;
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if (d10) state <= `state_idle;
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end
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end
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// Program reset key press
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// Program reset key press
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| Line 508... |
Line 544... |
err_sense_reset <= 0;
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err_sense_reset <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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end
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end
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// Hard reset
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`state_hard_reset_1: begin
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hard_reset <= 0;
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state <= `state_idle;
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end
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// Set storage entry switches
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// Set storage entry switches
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`state_storage_entry_sw_1: begin
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`state_storage_entry_sw_1: begin
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if (d0) begin
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if (d0) begin
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state <= `state_storage_entry_sw_2;
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state <= `state_storage_entry_sw_2;
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digit_ready <= 1;
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digit_ready <= 1;
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| Line 620... |
Line 662... |
gs_ram_addr <= gs_word_addr;
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gs_ram_addr <= gs_word_addr;
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state <= `state_read_gs_4;
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state <= `state_read_gs_4;
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end
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end
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`state_read_gs_4: begin
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`state_read_gs_4: begin
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cmd_digit_out <= gs_in;
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state <= `state_read_gs_5;
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state <= `state_read_gs_5;
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end
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end
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// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// 1 : Synchronize with d10
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// Turn on console_write_gs
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// 2 : Put a digit:
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// dx: blank
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// d0: minus
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// d1-d10: zero
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// gs_ram_addr++
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`state_clear_drum_1: begin
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if (d10) begin
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state <= `state_clear_drum_2;
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end
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end
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`state_clear_drum_2: begin
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write_gs <= 1;
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console_out <= dx? `biq_blank
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: d0? `biq_minus
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: `biq_0;
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if (write_gs)
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gs_ram_addr <= gs_ram_addr + 1;
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if (gs_ram_addr == 15'd23999) begin
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write_gs <= 0;
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state <= `state_idle;
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end
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end
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endcase;
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endcase;
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end
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end
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end;
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end;
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|
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always @(posedge rst, posedge ap) begin
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always @(posedge ap) begin
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if (rst) begin
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if (hard_reset) begin
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data_out <= `biq_blank;
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data_out <= `biq_blank;
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addr_out <= `biq_blank;
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addr_out <= `biq_blank;
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end else begin
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end else begin
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data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
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data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
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addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
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addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
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end
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end
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end;
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end;
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|
|
always @(posedge rst, posedge ap) begin
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always @(posedge ap) begin
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if (rst) begin
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if (hard_reset) begin
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punch_card <= 0;
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punch_card <= 0;
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read_card <= 0;
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read_card <= 0;
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card_digit_ready <= 0;
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card_digit_ready <= 0;
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end
|
end
|
end;
|
end;
|
