| Line 35... |
Line 35... |
input ap, dp,
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input ap, dp,
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input dx, d0, d1, d2, d3, d4, d5, d6, d10,
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input dx, d0, d1, d2, d3, d4, d5, d6, d10,
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input wu, hp,
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input wu, hp,
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input [0:3] early_idx, ontime_idx,
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input [0:3] early_idx, ontime_idx,
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input [0:6] cmd_digit_in, io_buffer_in, gs_in,
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input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
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prog_ontime,
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input [0:5] command,
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input [0:5] command,
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output reg[0:6] data_out, addr_out, console_out,
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output reg[0:6] data_out, addr_out, console_out,
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output [0:6] display_digit,
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output reg console_to_addr,
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output reg console_to_addr,
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output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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| Line 69... |
Line 71... |
assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
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assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
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assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
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assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
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assign ri_storage = disp_sw_ri;
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assign ri_storage = disp_sw_ri;
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assign ro_storage = disp_sw_ro;
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assign ro_storage = disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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assign display_digit = (disp_sw_lacc | disp_sw_uacc)? acc_ontime
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: (disp_sw_dist | disp_sw_ri | disp_sw_ro)? dist_ontime
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: disp_sw_pgm? prog_ontime
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: `biq_blank;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Calculate the RAM address of the general storage word at address gs_addr_.
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// Calculate the RAM address of the general storage word at address gs_addr_.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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| Line 128... |
Line 134... |
`define state_write_gs_5 6'd40
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`define state_write_gs_5 6'd40
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`define state_clear_drum_1 6'd41
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`define state_clear_drum_1 6'd41
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`define state_clear_drum_2 6'd42
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`define state_clear_drum_2 6'd42
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`define state_clear_drum_3 6'd43
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`define state_clear_drum_3 6'd43
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`define state_load_gs_1 6'd44
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`define state_load_gs_1 6'd44
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`define state_load_gs_1 6'd45
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`define state_load_gs_2 6'd45
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`define state_dump_gs_1 6'd46
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`define state_dump_gs_2 6'd47
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`define state_dump_gs_3 6'd48
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`define state_dump_gs_4 6'd49
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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| Line 450... |
Line 460... |
if (ctl_sw_manual) begin
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if (ctl_sw_manual) begin
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busy <= 1;
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busy <= 1;
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state <= `state_write_gs_1;
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state <= `state_write_gs_1;
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end
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end
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end
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end
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end
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`cmd_read_acc: begin
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`cmd_read_acc: begin
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end
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end
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| Line 487... |
Line 496... |
digit_ready <= 1;
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digit_ready <= 1;
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end
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end
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end
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end
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`cmd_dump_gs: begin
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`cmd_dump_gs: begin
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if (ctl_sw_manual) begin
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busy <= 1;
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state <= `state_dump_gs_1;
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end
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end
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end
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`cmd_power_on_reset: begin
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`cmd_power_on_reset: begin
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busy <= 1;
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busy <= 1;
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do_power_on_reset <= 1;
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do_power_on_reset <= 1;
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| Line 701... |
Line 714... |
end
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end
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end
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end
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`state_read_gs_4: begin
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`state_read_gs_4: begin
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state <= `state_read_gs_5;
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state <= `state_read_gs_5;
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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end
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end
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`state_read_gs_5: begin
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`state_read_gs_5: begin
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digit_ready <= 1;
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digit_ready <= 1;
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cmd_digit_out <= gs_in;
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cmd_digit_out <= gs_in;
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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if (dx) begin
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if (dx) begin
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state <= `state_read_gs_6;
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state <= `state_read_gs_6;
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read_gs <= 0;
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read_gs <= 0;
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end
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end
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end
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end
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| Line 761... |
Line 774... |
end
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end
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`state_write_gs_4: begin
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`state_write_gs_4: begin
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write_gs <= 1;
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write_gs <= 1;
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console_out <= cmd_digit_in;
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console_out <= cmd_digit_in;
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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if (d10) begin
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if (d10) begin
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digit_ready <= 0;
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digit_ready <= 0;
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state <= `state_write_gs_5;
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state <= `state_write_gs_5;
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end
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end
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end
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end
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| Line 774... |
Line 787... |
write_gs <= 0;
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write_gs <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// 1 : Synchronize with dx
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// 1 : Synchronize with d10
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// Put first dx digit
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// Turn on console_write_gs
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// 2 : Put a digit:
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// 2 : Put a digit:
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// dx: blank
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// dx: blank
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// d0: minus
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// d0: minus
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// d1-d10: zero
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// d1-d10: zero
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// gs_ram_addr++
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`state_clear_drum_1: begin
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`state_clear_drum_1: begin
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if (d10) begin
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if (dx) begin
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console_out <= `biq_blank;
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console_out <= `biq_blank;
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gs_ram_addr <= 15'd0;
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gs_ram_addr <= 15'd0;
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write_gs <= 1;
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write_gs <= 1;
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state <= `state_clear_drum_2;
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state <= `state_clear_drum_2;
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end
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end
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| Line 795... |
Line 806... |
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`state_clear_drum_2: begin
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`state_clear_drum_2: begin
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console_out <= dx? `biq_blank
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console_out <= dx? `biq_blank
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: d0? `biq_minus
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: d0? `biq_minus
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: `biq_0;
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: `biq_0;
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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if (gs_ram_addr == 15'd23999) begin
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if (gs_ram_addr == 15'd23999) begin
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write_gs <= 0;
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write_gs <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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end
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end
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| Line 810... |
Line 821... |
console_out <= cmd_digit_in;
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console_out <= cmd_digit_in;
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state <= `state_load_gs_2;
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state <= `state_load_gs_2;
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end
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end
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`state_load_gs_2: begin
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`state_load_gs_2: begin
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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console_out <= cmd_digit_in;
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console_out <= cmd_digit_in;
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if (gs_ram_addr == 15d'23999) begin
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if (gs_ram_addr == 15'd23999) begin
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write_gs <= 0;
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write_gs <= 0;
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digit_ready <= 0;
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digit_ready <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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end
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end
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`state_dump_gs_1: begin
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gs_ram_addr <= 15'd0;
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read_gs <= 1;
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state <= `state_dump_gs_2;
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end
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`state_dump_gs_2: begin
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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state <= `state_dump_gs_3;
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end
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`state_dump_gs_3: begin
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digit_ready <= 1;
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gs_ram_addr <= (gs_ram_addr + 1) % 32768;
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cmd_digit_out <= gs_in;
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if (gs_ram_addr == 15'd23999) begin
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state <= `state_dump_gs_4;
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end
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end
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`state_dump_gs_4: begin
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digit_ready <= 0;
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read_gs <= 0;
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state <= `state_idle;
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end
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endcase;
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endcase;
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end
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end
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end;
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end;
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always @(posedge ap) begin
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always @(posedge ap) begin
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