| Line 35... |
Line 35... |
input rst,
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input rst,
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|
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input [0:6] cmd_digit_in, io_buffer_in,
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input [0:6] cmd_digit_in, io_buffer_in,
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input [0:5] command,
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input [0:5] command,
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|
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output [0:6] cmd_digit_out,
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output [0:6] cmd_digit_out, display_digit,
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output busy, digit_ready, punch_card, read_card, card_digit_ready,
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output busy, digit_ready, punch_card, read_card, card_digit_ready,
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output synch
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output digit_sync, word_upper,
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output [0:3] digit_ctr
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);
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);
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|
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wire ap, bp, cp, dp;
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wire ap, bp, cp, dp;
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wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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| Line 50... |
Line 51... |
wl, wu, ewl;
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wl, wu, ewl;
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wire s0, s1, s2, s3, s4, hp;
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wire s0, s1, s2, s3, s4, hp;
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wire [0:9] digit_idx;
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wire [0:9] digit_idx;
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wire [0:3] early_idx, ontime_idx;
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wire [0:3] early_idx, ontime_idx;
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|
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assign synch = bp;
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assign digit_sync = bp;
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assign digit_ctr = ontime_idx;
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assign word_upper = wu;
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|
|
timing tm (
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timing tm (
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.ap(ap),
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.ap(ap),
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| Line 110... |
Line 113... |
.early_idx(early_idx),
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.early_idx(early_idx),
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.ontime_idx(ontime_idx)
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.ontime_idx(ontime_idx)
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);
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);
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
|
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// Accumulator
|
|
//-----------------------------------------------------------------------------
|
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wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out;
|
|
|
|
//-----------------------------------------------------------------------------
|
// General storage
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// General storage
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//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
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wire [0:4] gs_out;
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wire [0:4] gs_out;
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wire gs_double_write, gs_no_write;
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wire gs_double_write, gs_no_write;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Operator controls
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// Operator controls
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//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire [0:6] oc_data_out, oc_addr_out, oc_console_out;
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wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit;
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wire oc_console_to_addr;
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wire oc_console_to_addr;
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wire [0:14] oc_gs_ram_addr;
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wire [0:14] oc_gs_ram_addr;
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wire oc_read_gs, oc_write_gs;
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wire oc_read_gs, oc_write_gs;
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wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
|
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
|
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
|
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
|
oc_storage_control;
|
oc_storage_control;
|
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
|
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
|
oc_hard_reset;
|
oc_hard_reset;
|
|
assign display_digit = oc_display_digit;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Translators
|
// Translators
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire tr_gs_write;
|
wire tr_gs_write;
|
wire [0:4] tr_gs_in;
|
wire [0:4] tr_gs_in;
|
wire [0:6] tr_select_out;
|
wire [0:6] tr_select_out;
|
|
|
|
accumulator ac (
|
|
.rst(rst),
|
|
.ap(ap),
|
|
.bp(bp),
|
|
.dp(dp),
|
|
.d1(d1),
|
|
.d2(d2),
|
|
.d10(d10),
|
|
.dxu(dxu),
|
|
.d0u(d0u),
|
|
.wu(wu),
|
|
.wl(wl),
|
|
.adder_out(`biq_0),
|
|
.acc_regen_gate(1'b1),
|
|
.right_shift_gate(1'b0),
|
|
.acc_ri_gate(1'b0),
|
|
.zero_shift_count(1'b0),
|
|
.man_acc_reset(oc_man_acc_reset),
|
|
.reset_op_latch(1'b0),
|
|
.early_idx(early_idx),
|
|
.ontime_idx(ontime_idx),
|
|
.early_out(ac_early_out),
|
|
.ontime_out(ac_ontime_out),
|
|
.ped_out(ac_ped_out)
|
|
);
|
|
|
gen_store gs (
|
gen_store gs (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
.ap(ap),
|
.ap(ap),
|
.dp(dp),
|
.dp(dp),
|
.write_gate(tr_gs_write),
|
.write_gate(tr_gs_write),
|
| Line 174... |
Line 209... |
.early_idx(early_idx),
|
.early_idx(early_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_idx(ontime_idx),
|
.cmd_digit_in(cmd_digit_in),
|
.cmd_digit_in(cmd_digit_in),
|
.io_buffer_in(io_buffer_in),
|
.io_buffer_in(io_buffer_in),
|
.gs_in(tr_select_out),
|
.gs_in(tr_select_out),
|
|
.acc_ontime(ac_ontime_out),
|
|
.dist_ontime(`biq_blank),
|
|
.prog_ontime(`biq_blank),
|
.command(command),
|
.command(command),
|
.data_out(oc_data_out),
|
.data_out(oc_data_out),
|
.addr_out(oc_addr_out),
|
.addr_out(oc_addr_out),
|
.console_out(oc_console_out),
|
.console_out(oc_console_out),
|
|
.display_digit(oc_display_digit),
|
.console_to_addr(oc_console_to_addr),
|
.console_to_addr(oc_console_to_addr),
|
.gs_ram_addr(oc_gs_ram_addr),
|
.gs_ram_addr(oc_gs_ram_addr),
|
.read_gs(oc_read_gs),
|
.read_gs(oc_read_gs),
|
.write_gs(oc_write_gs),
|
.write_gs(oc_write_gs),
|
.pgm_start(oc_pgm_start),
|
.pgm_start(oc_pgm_start),
|
