`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 23:02:15 11/13/2009
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// Create Date: 23:02:15 11/13/2009
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// Design Name:
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// Design Name:
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// Module Name: iotools
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// Module Name: iotools
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module porta(dataout, datain, mode, extinout);
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module porta(dataout, datain, mode, extinout);
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output [7:0] dataout;
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output [7:0] dataout;
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input [7:0] datain;
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input [7:0] datain;
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input mode;
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input mode;
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inout [7:0] extinout;
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inout [7:0] extinout;
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assign dataout=(mode==1)?extinout:8'bz; //input to i8255
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assign dataout=(mode==1)?extinout:8'bz; //input to i8255
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assign extinout=(mode==0)?datain:8'bz; //output
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assign extinout=(mode==0)?datain:8'bz; //output
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endmodule
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endmodule
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module portb(dataout, datain, mode, extinout);
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module portb(dataout, datain, mode, extinout);
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output [7:0] dataout;
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output [7:0] dataout;
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input [7:0] datain;
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input [7:0] datain;
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input mode;
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input mode;
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inout [7:0] extinout;
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inout [7:0] extinout;
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assign dataout=(mode==1)?extinout:8'bz;
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assign dataout=(mode==1)?extinout:8'bz;
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assign extinout=(mode==0)?datain:8'bz;
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assign extinout=(mode==0)?datain:8'bz;
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endmodule
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endmodule
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module portc(dataout, datain, mode, extinout);
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module portc(dataout, datain, mode, extinout);
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output [3:0] dataout;
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output [3:0] dataout;
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input [3:0] datain;
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input [3:0] datain;
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input [3:0] mode;
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input [3:0] mode;
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inout [3:0] extinout;
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inout [3:0] extinout;
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assign dataout[0:0]=(mode[0:0])?extinout[0:0]:1'bz;
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assign dataout[0:0]=(mode[0:0])?extinout[0:0]:1'bz;
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assign dataout[1:1]=(mode[1:1])?extinout[1:1]:1'bz;
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assign dataout[1:1]=(mode[1:1])?extinout[1:1]:1'bz;
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assign dataout[2:2]=(mode[2:2])?extinout[2:2]:1'bz;
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assign dataout[2:2]=(mode[2:2])?extinout[2:2]:1'bz;
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assign dataout[3:3]=(mode[3:3])?extinout[3:3]:1'bz;
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assign dataout[3:3]=(mode[3:3])?extinout[3:3]:1'bz;
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assign extinout[0:0]=(mode[0:0])?1'bz:datain[0:0];
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assign extinout[0:0]=(mode[0:0])?1'bz:datain[0:0];
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assign extinout[1:1]=(mode[1:1])?1'bz:datain[1:1];
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assign extinout[1:1]=(mode[1:1])?1'bz:datain[1:1];
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assign extinout[2:2]=(mode[2:2])?1'bz:datain[2:2];
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assign extinout[2:2]=(mode[2:2])?1'bz:datain[2:2];
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assign extinout[3:3]=(mode[3:3])?1'bz:datain[3:3];
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assign extinout[3:3]=(mode[3:3])?1'bz:datain[3:3];
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endmodule
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endmodule
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module pactl(dataout, datain, portaio, portcio, signals, cw, sel);
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module pactl(dataout, datain, portaio, portcio, signals, cw, sel);
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//Group A control
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//Group A control
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output [7:0] dataout;
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output [7:0] dataout;
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output reg [3:0] signals;
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output reg [3:0] signals;
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input [7:0] datain;
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input [7:0] datain;
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inout [7:0] portaio; //external port
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inout [7:0] portaio; //external port
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inout [3:0] portcio; //-//-
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inout [3:0] portcio; //-//-
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input [3:0] cw; //control word
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input [3:0] cw; //control word
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input [1:0] sel; //selection
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input [1:0] sel; //selection
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wire [7:0] portadatain;
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wire [7:0] portadatain;
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reg [7:0] portadataout;
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reg [7:0] portadataout;
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wire [3:0] portcdatain;
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wire [3:0] portcdatain;
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reg [3:0] portcdataout;
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reg [3:0] portcdataout;
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reg oflag; //control a input to i8255 core
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reg oflag; //control a input to i8255 core
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reg ocflag; //control c input
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reg ocflag; //control c input
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reg [7:0] buffer; //internal latch
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reg [7:0] buffer; //internal latch
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reg [3:0] cbuffer; //internal latch for port c
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reg [3:0] cbuffer; //internal latch for port c
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reg [3:0] pccw; //control each of 4 wires of port c
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reg [3:0] pccw; //control each of 4 wires of port c
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reg pacw; //0-output, 1 -input
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reg pacw; //0-output, 1 -input
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reg [3:0] pcio;
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reg [3:0] pcio;
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reg bitctl;
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reg bitctl;
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reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
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reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
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reg awflag; //external output enabled
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reg awflag; //external output enabled
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reg cwflag; //-//-
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reg cwflag; //-//-
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porta pa1(.dataout(portadatain), .datain(portadataout), .mode(pacw), .extinout(portaio));
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porta pa1(.dataout(portadatain), .datain(portadataout), .mode(pacw), .extinout(portaio));
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portc pch(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
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portc pch(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
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//read data to internal bus supports latches
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//read data to internal bus supports latches
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assign dataout=(oflag)?(intmode==0)?portadatain:
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assign dataout=(oflag)?(intmode==0)?portadatain:
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buffer:(ocflag)?(intmode==0)?{portcdatain, 4'bz}:
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buffer:(ocflag)?(intmode==0)?{portcdatain, 4'bz}:
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{cbuffer, 4'bz}:8'bz;
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{cbuffer, 4'bz}:8'bz;
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//assign portadata=(awflag)?buffer:8'bz; //send data to porta
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//assign portadata=(awflag)?buffer:8'bz; //send data to porta
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//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
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//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
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always @(negedge sel[0:0]) begin
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always @(negedge sel[0:0]) begin
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oflag<=0;
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oflag<=0;
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ocflag<=0;
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ocflag<=0;
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end
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end
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always @(posedge sel[0:0]) begin
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always @(posedge sel[0:0]) begin
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case (cw)
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case (cw)
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4'h1: begin //write cw
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4'h1: begin //write cw
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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awflag=0;
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awflag=0;
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cwflag=0;
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cwflag=0;
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//wait_data();
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//wait_data();
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if (datain[7:7]==0) begin
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if (datain[7:7]==0) begin
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//set bits in port c
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//set bits in port c
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if (datain[0:0]) bitctl=1;
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if (datain[0:0]) bitctl=1;
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else bitctl=0;
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else bitctl=0;
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case(datain[3:1])
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case(datain[3:1])
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3'b000: pcio[0:0]=bitctl;
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3'b000: pcio[0:0]=bitctl;
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3'b001: pcio[1:1]=bitctl;
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3'b001: pcio[1:1]=bitctl;
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3'b010: pcio[2:2]=bitctl;
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3'b010: pcio[2:2]=bitctl;
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3'b011: pcio[3:3]=bitctl;
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3'b011: pcio[3:3]=bitctl;
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default: pcio=0;
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default: pcio=0;
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endcase
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endcase
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end
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end
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else begin
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else begin
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//setup group
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//setup group
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case (datain[6:5])
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case (datain[6:5])
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2'b00: begin
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2'b00: begin
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//simple io mode
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//simple io mode
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intmode=0; //no latched input
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intmode=0; //no latched input
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pacw=datain[4:4];
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pacw=datain[4:4];
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awflag=~pacw;
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awflag=~pacw;
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if (pacw==0) portadataout=0;
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if (pacw==0) portadataout=0;
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if (datain[3:3]==0) begin
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if (datain[3:3]==0) begin
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pccw=0;
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pccw=0;
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portcdataout=0;
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portcdataout=0;
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end
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end
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else begin
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else begin
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pccw=4'b1111;
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pccw=4'b1111;
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end
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end
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cwflag=~datain[3:3];
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cwflag=~datain[3:3];
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end
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end
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2'b01: begin
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2'b01: begin
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intmode=1;
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intmode=1;
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pccw[0:0]=0;//intrb-->
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pccw[0:0]=0;//intrb-->
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pccw[1:1]=0;//ibfb-->
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pccw[1:1]=0;//ibfb-->
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pccw[2:2]=1;//nSTBB<--
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pccw[2:2]=1;//nSTBB<--
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pccw[3:3]=0;//no val
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pccw[3:3]=0;//no val
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end
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end
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2'b10: intmode=2;
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2'b10: intmode=2;
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default: intmode=2;
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default: intmode=2;
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endcase
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endcase
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end
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end
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end
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end
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4'h2: begin //write port a
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4'h2: begin //write port a
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portadataout=datain;
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portadataout=datain;
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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awflag=1;
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awflag=1;
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end
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end
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4'h3: begin //read port a
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4'h3: begin //read port a
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if (intmode!=0) buffer=portadatain;
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if (intmode!=0) buffer=portadatain;
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awflag=0;
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awflag=0;
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oflag=1;
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oflag=1;
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end
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end
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4'h4: begin //write port c
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4'h4: begin //write port c
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portcdataout=datain[7:4];
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portcdataout=datain[7:4];
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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cwflag=1;
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cwflag=1;
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end
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end
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4'h5: begin //read port c
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4'h5: begin //read port c
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if(intmode!=0) cbuffer=portcdatain;
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if(intmode!=0) cbuffer=portcdatain;
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cwflag=0;
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cwflag=0;
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oflag=0;
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oflag=0;
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ocflag=1;
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ocflag=1;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module pbctl(dataout, datain, portbio, portcio, signals, cw, sel);
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module pbctl(dataout, datain, portbio, portcio, signals, cw, sel);
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//Group B control
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//Group B control
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output [7:0] dataout;
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output [7:0] dataout;
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output reg [3:0] signals;
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output reg [3:0] signals;
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input [7:0] datain;
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input [7:0] datain;
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inout [7:0] portbio; //external port
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inout [7:0] portbio; //external port
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inout [3:0] portcio; //-//-
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inout [3:0] portcio; //-//-
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input [3:0] cw; //control word
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input [3:0] cw; //control word
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input [1:0] sel; //selection
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input [1:0] sel; //selection
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wire [7:0] portbdatain;
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wire [7:0] portbdatain;
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reg [7:0] portbdataout;
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reg [7:0] portbdataout;
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wire [3:0] portcdatain;
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wire [3:0] portcdatain;
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reg [3:0] portcdataout;
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reg [3:0] portcdataout;
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reg oflag; //control a input to i8255 core
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reg oflag; //control a input to i8255 core
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reg ocflag; //control c input
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reg ocflag; //control c input
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reg [7:0] buffer; //internal latch
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reg [7:0] buffer; //internal latch
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reg [3:0] cbuffer; //internal latch for port c
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reg [3:0] cbuffer; //internal latch for port c
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reg [3:0] pccw; //control each of 4 wires of port c
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reg [3:0] pccw; //control each of 4 wires of port c
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reg pbcw; //0-output, 1 -input
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reg pbcw; //0-output, 1 -input
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reg [3:0] pcio;
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reg [3:0] pcio;
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reg bitctl;
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reg bitctl;
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reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
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reg [1:0] intmode; //mode:0-normal, 1- strob, 2-extra
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reg bwflag; //external output enabled
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reg bwflag; //external output enabled
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reg cwflag; //-//-
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reg cwflag; //-//-
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porta pb1(.dataout(portbdatain), .datain(portbdataout), .mode(pbcw), .extinout(portbio));
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porta pb1(.dataout(portbdatain), .datain(portbdataout), .mode(pbcw), .extinout(portbio));
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portc pcl(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
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portc pcl(.dataout(portcdatain), .datain(portcdataout), .mode(pccw), .extinout(portcio));
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//read data to internal bus supports latches
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//read data to internal bus supports latches
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assign dataout=(oflag)?(intmode==0)?portbdatain:
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assign dataout=(oflag)?(intmode==0)?portbdatain:
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buffer:(ocflag)?(intmode==0)?{4'bz, portcdatain}:
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buffer:(ocflag)?(intmode==0)?{4'bz, portcdatain}:
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{4'bz, cbuffer}:8'bz;
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{4'bz, cbuffer}:8'bz;
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//assign portbdata=(bwflag)?buffer:8'bz; //send data to porta
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//assign portbdata=(bwflag)?buffer:8'bz; //send data to porta
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//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
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//assign portcdata=(cwflag)?cbuffer:4'bz;//send data to hight 4 bits of port c
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always @(negedge sel[1:1]) begin
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always @(negedge sel[1:1]) begin
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oflag<=0;
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oflag<=0;
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ocflag<=0;
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ocflag<=0;
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end
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end
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always @(posedge sel[1:1]) begin
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always @(posedge sel[1:1]) begin
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case (cw)
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case (cw)
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4'h1: begin //write cw
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4'h1: begin //write cw
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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bwflag=0;
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bwflag=0;
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cwflag=0;
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cwflag=0;
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if (datain[7:7]==0) begin
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if (datain[7:7]==0) begin
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//set bits in port c
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//set bits in port c
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if (datain[0:0]) bitctl=1;
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if (datain[0:0]) bitctl=1;
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else bitctl=0;
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else bitctl=0;
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case(datain[3:1])
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case(datain[3:1])
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3'b100: pcio[0:0]=bitctl;
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3'b100: pcio[0:0]=bitctl;
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3'b101: pcio[1:1]=bitctl;
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3'b101: pcio[1:1]=bitctl;
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3'b110: pcio[2:2]=bitctl;
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3'b110: pcio[2:2]=bitctl;
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3'b111: pcio[3:3]=bitctl;
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3'b111: pcio[3:3]=bitctl;
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default: pcio=0;
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default: pcio=0;
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endcase
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endcase
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end
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end
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else begin
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else begin
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//setup group
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//setup group
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case (datain[2:2])
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case (datain[2:2])
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1'b0: begin
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1'b0: begin
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//simple io mode
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//simple io mode
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intmode=0; //no latched input
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intmode=0; //no latched input
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pbcw=datain[1:1];
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pbcw=datain[1:1];
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bwflag=~pbcw;
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bwflag=~pbcw;
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if (pbcw==0) portbdataout=0;
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if (pbcw==0) portbdataout=0;
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if (datain[0:0]==0) begin
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if (datain[0:0]==0) begin
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pccw=0;
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pccw=0;
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portcdataout=0;
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portcdataout=0;
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end
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end
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else begin
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else begin
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pccw=4'b1111;
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pccw=4'b1111;
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end
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end
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cwflag=~datain[0:0];
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cwflag=~datain[0:0];
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end
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end
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1'b01: begin
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1'b01: begin
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intmode=1;
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intmode=1;
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pccw[0:0]=0;//intrb-->
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pccw[0:0]=0;//intrb-->
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pccw[1:1]=0;//ibfb-->
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pccw[1:1]=0;//ibfb-->
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pccw[2:2]=1;//nSTBB<--
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pccw[2:2]=1;//nSTBB<--
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pccw[3:3]=0;//no val
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pccw[3:3]=0;//no val
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end
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end
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default: intmode=1;
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default: intmode=1;
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endcase
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endcase
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end
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end
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end
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end
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4'h2: begin //write port a
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4'h2: begin //write port a
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portbdataout=datain;
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portbdataout=datain;
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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bwflag=1;
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bwflag=1;
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end
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end
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4'h3: begin //read port a
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4'h3: begin //read port a
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if (intmode!=0) buffer=portbdatain;
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if (intmode!=0) buffer=portbdatain;
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bwflag=0;
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bwflag=0;
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oflag=1;
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oflag=1;
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end
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end
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4'h4: begin //write port c
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4'h4: begin //write port c
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portcdataout=datain[3:0];
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portcdataout=datain[3:0];
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oflag=0;
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oflag=0;
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ocflag=0;
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ocflag=0;
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cwflag=1;
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cwflag=1;
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end
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end
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4'h5: begin //read port c
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4'h5: begin //read port c
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if(intmode!=0) cbuffer=portcdatain;
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if(intmode!=0) cbuffer=portcdatain;
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cwflag=0;
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cwflag=0;
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oflag=0;
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oflag=0;
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ocflag=1;
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ocflag=1;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module i8255(data, reset, ncs, nrd, nwr, addr, pa, pb, pch, pcl);
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module i8255(data, reset, ncs, nrd, nwr, addr, pa, pb, pch, pcl);
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//main trigger events is nrd and nwr
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//main trigger events is nrd and nwr
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//after all operation this ones must be set to 1 both
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//after all operation this ones must be set to 1 both
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//ncs - selects device
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//ncs - selects device
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//WARNING:
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//WARNING:
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//you must setup 'data' bus first before sending nWR
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//you must setup 'data' bus first before sending nWR
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//because iSIM has issue with inout assignment delay
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//because iSIM has issue with inout assignment delay
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inout [7:0] data; //data to/from chip
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inout [7:0] data; //data to/from chip
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input reset;
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input reset;
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input ncs; //inverted CS
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input ncs; //inverted CS
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input nrd; //inverted RD
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input nrd; //inverted RD
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input nwr; //inverted WR
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input nwr; //inverted WR
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input [1:0] addr; //2 bits addr(A0,A1)
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input [1:0] addr; //2 bits addr(A0,A1)
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inout [7:0] pa; //port a
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inout [7:0] pa; //port a
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inout [7:0] pb; //port b
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inout [7:0] pb; //port b
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inout [3:0] pch; //port c hight 4 bits
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inout [3:0] pch; //port c hight 4 bits
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inout [3:0] pcl; //port c low 4 bits
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inout [3:0] pcl; //port c low 4 bits
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reg [1:0] firststep;
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reg [1:0] firststep;
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reg [2:0] nextstep;
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reg [2:0] nextstep;
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reg [7:0] mode;
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reg [7:0] mode;
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wire [7:0] bufferin;
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wire [7:0] bufferin;
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reg [7:0] bufferout;
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reg [7:0] bufferout;
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reg [7:0] intdata;
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reg [7:0] intdata;
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reg iflag; //move to 'data'
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reg iflag; //move to 'data'
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reg oflag; //output to 'buffer'
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reg oflag; //output to 'buffer'
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reg extrai;
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reg extrai;
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reg extrao;
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reg extrao;
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reg [1:0] sel;
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reg [1:0] sel;
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//wire [7:0] odata;
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//wire [7:0] odata;
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//group A
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//group A
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wire [3:0] grasigs;
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wire [3:0] grasigs;
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reg [3:0] gracw;
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reg [3:0] gracw;
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//group B
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//group B
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wire [3:0] grbsigs;
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wire [3:0] grbsigs;
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reg [3:0] grbcw;
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reg [3:0] grbcw;
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assign data=(iflag)?bufferin:(extrai)?intdata:8'bz;
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assign data=(iflag)?bufferin:(extrai)?intdata:8'bz;
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pactl grpa(.dataout(bufferin), .datain(bufferout), .portaio(pa), .portcio(pch),
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pactl grpa(.dataout(bufferin), .datain(bufferout), .portaio(pa), .portcio(pch),
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.signals(grasigs), .cw(gracw), .sel(sel));
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.signals(grasigs), .cw(gracw), .sel(sel));
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pbctl grpb(.dataout(bufferin), .datain(bufferout), .portbio(pb), .portcio(pcl),
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pbctl grpb(.dataout(bufferin), .datain(bufferout), .portbio(pb), .portcio(pcl),
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.signals(grbsigs), .cw(grbcw), .sel(sel));
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.signals(grbsigs), .cw(grbcw), .sel(sel));
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always @(posedge reset) begin
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always @(posedge reset) begin
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oflag<=0;
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oflag<=0;
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extrao<=1;
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extrao<=1;
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mode<=8'h9b;
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mode<=8'h9b;
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firststep<=0;
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firststep<=0;
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nextstep<=0;
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nextstep<=0;
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iflag<=0;
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iflag<=0;
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extrai<=0;
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extrai<=0;
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intdata<=8'h9b;
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intdata<=8'h9b;
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gracw<=1;//init group A
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gracw<=1;//init group A
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grbcw<=1;//init group B
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grbcw<=1;//init group B
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bufferout=8'h9b;
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bufferout=8'h9b;
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sel<=3;
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sel<=3;
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end
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end
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always @(negedge reset) begin
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always @(negedge reset) begin
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sel<=0;
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sel<=0;
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extrai<=0;
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extrai<=0;
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extrao<=0;
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extrao<=0;
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gracw<=0;
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gracw<=0;
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grbcw<=0;
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grbcw<=0;
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end
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end
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always @(negedge nwr) begin
|
always @(negedge nwr) begin
|
//write event
|
//write event
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if(ncs==0) begin
|
if(ncs==0) begin
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case(addr)
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case(addr)
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//control register
|
//control register
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2'b11: begin //write - control
|
2'b11: begin //write - control
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if (data[7:7]==0) begin
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if (data[7:7]==0) begin
|
gracw=1;
|
gracw<=1;
|
end
|
end
|
else begin
|
else begin
|
//send mode to the all groups
|
//send mode to the all groups
|
iflag<=0;
|
iflag<=0;
|
extrai<=0;
|
extrai<=0;
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oflag<=0;
|
oflag<=0;
|
mode<=data;
|
mode<=data;
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intdata<=data;
|
intdata<=data;
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bufferout<=data;
|
bufferout<=data;
|
gracw<=1;
|
gracw<=1;
|
grbcw<=1;
|
grbcw<=1;
|
sel<=3;
|
sel<=3;
|
end
|
end
|
end
|
end
|
2'b00: begin//write - porta
|
2'b00: begin//write - porta
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$display("Value: %b", data);
|
$display("Value: %b", data);
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oflag<=1;
|
oflag<=1;
|
gracw<=2;
|
gracw<=2;
|
bufferout<=data;
|
bufferout<=data;
|
sel<=3;
|
sel<=3;
|
end
|
end
|
2'b01: begin //write - portb
|
2'b01: begin //write - portb
|
oflag<=1;
|
oflag<=1;
|
grbcw<=2;
|
grbcw<=2;
|
bufferout<=data;
|
bufferout<=data;
|
sel<=3;
|
sel<=3;
|
end
|
end
|
2'b10: begin//write - portc
|
2'b10: begin//write - portc
|
oflag<=1;
|
oflag<=1;
|
gracw<=4;
|
gracw<=4;
|
grbcw<=4;
|
grbcw<=4;
|
bufferout<=data;
|
bufferout<=data;
|
sel<=3;
|
sel<=3;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
always @(posedge nwr) begin
|
always @(posedge nwr) begin
|
//write completed event
|
//write completed event
|
if(ncs==0) begin
|
if(ncs==0) begin
|
extrao<=0;
|
extrao<=0;
|
extrai<=0;
|
extrai<=0;
|
firststep<=0;
|
firststep<=0;
|
nextstep<=0;
|
nextstep<=0;
|
iflag<=0;
|
iflag<=0;
|
oflag<=0;
|
oflag<=0;
|
gracw<=0;
|
gracw<=0;
|
grbcw<=0;
|
grbcw<=0;
|
sel<=0;
|
sel<=0;
|
end
|
end
|
end
|
end
|
always @(negedge nrd) begin
|
always @(negedge nrd) begin
|
//read event
|
//read event
|
if(ncs==0) begin
|
if(ncs==0) begin
|
case (addr)
|
case (addr)
|
2'b11: begin//read - control
|
2'b11: begin//read - control
|
intdata=mode;
|
intdata<=mode;
|
iflag=0;
|
iflag<=0;
|
oflag=0;
|
oflag<=0;
|
extrai=1;
|
extrai<=1;
|
end
|
end
|
2'b00: begin //read - porta
|
2'b00: begin //read - porta
|
iflag=1;
|
iflag<=1;
|
gracw=3;
|
gracw<=3;
|
sel=1;
|
sel<=1;
|
end
|
end
|
2'b01: begin//read - portb
|
2'b01: begin//read - portb
|
iflag=1;
|
iflag<=1;
|
grbcw=3;
|
grbcw<=3;
|
sel=1;
|
sel<=1;
|
end
|
end
|
2'b10: begin//read - portc
|
2'b10: begin//read - portc
|
iflag=1;
|
iflag<=1;
|
gracw=5;
|
gracw<=5;
|
grbcw=5;
|
grbcw<=5;
|
sel=3;
|
sel<=3;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
always @(posedge nrd) begin
|
always @(posedge nrd) begin
|
//read completed event
|
//read completed event
|
if(ncs==0) begin
|
if(ncs==0) begin
|
extrao<=0;
|
extrao<=0;
|
extrai<=0;
|
extrai<=0;
|
firststep<=0;
|
firststep<=0;
|
nextstep<=0;
|
nextstep<=0;
|
iflag<=0;
|
iflag<=0;
|
oflag<=0;
|
oflag<=0;
|
gracw<=0;
|
gracw<=0;
|
grbcw<=0;
|
grbcw<=0;
|
sel<=0;
|
sel<=0;
|
end
|
end
|
end
|
end
|
|
|
