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https://opencores.org/ocsvn/i8255/i8255/trunk
[/] [i8255/] [tsti8255.v] - Diff between revs 2 and 3
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| Rev 2 |
Rev 3 |
| Line 68... |
Line 68... |
// Initialize Inputs
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// Initialize Inputs
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reset <= 1;
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reset <= 1;
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pae<=0;
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pae<=0;
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pche<=0;
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pche<=0;
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wrtport<=0;
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wrtport<=0;
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pause<=0;
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ncs <= 1;
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ncs <= 1;
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nrd <= 1;
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nrd <= 1;
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nwr <= 1;
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nwr <= 1;
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addr <= 2'b11;
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addr <= 2'b11;
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oflag<=0;
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oflag<=0;
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| Line 111... |
Line 110... |
step<=33;
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step<=33;
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resetret<=3;
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resetret<=3;
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writeret<=32;
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writeret<=32;
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end
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end
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3: begin
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3: begin
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newval=8'h0;
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newval<=8'h0;
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nrd=1;
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nrd<=1;
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nwr=1;
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nwr<=1;
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step=4;
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step<=4;
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end
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end
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4: begin
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4: begin
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newval=8'b10100000;
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newval<=8'b10100000;
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addr=2;
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addr<=2;
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nrd=1;
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nrd<=1;
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nwr=0;
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nwr<=0;
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step=5;
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step<=5;
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end
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end
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6: begin
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6: begin
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newval=8'b10010000; //a-output, c -input //#4
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newval<=8'b10010000; //a-output, c -input //#4
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addr=3;
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addr<=3;
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oflag=1;
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oflag<=1;
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pae=0;
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pae<=0;
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step=33;
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step<=33;
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resetret=7;
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resetret<=7;
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writeret=32;
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writeret<=32;
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end
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end
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7: begin
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7: begin
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wrtport=8'b11010000; //#10
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wrtport<=8'b11010000; //#10
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pae=1;
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pae<=1;
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//pche=1;
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//pche=1;
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oflag=0;
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oflag<=0;
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addr=0;
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addr<=0;
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nrd=0;
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nrd<=0;
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nwr=1;
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nwr<=1;
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step=32;
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step<=32;
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resetret=8;
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resetret<=8;
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end
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end
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8: begin
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8: begin
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newval=8'b10100000;
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newval<=8'b10100000;
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//pae=0;
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//pae=0;
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pche=1;
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pche<=1;
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oflag=1;
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oflag<=1;
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addr=0;
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addr<=0;
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nrd=1;
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nrd<=1;
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nwr=0;
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nwr<=0;
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step=10;
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step<=10;
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end
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end
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9: begin
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9: begin
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pae=0;
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pae<=0;
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addr=0;
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addr<=0;
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nrd=0;
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nrd<=0;
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nwr=1;
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nwr<=1;
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step=10;
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step<=10;
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end
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end
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32: begin
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32: begin //reset step
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oflag=0;
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oflag<=0;
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nrd=1;
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nrd<=1;
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nwr=1;
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nwr<=1;
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step=resetret;
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step<=resetret;
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end
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end
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33: begin //write routine
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33: begin //write routine
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nwr=0;
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nwr<=0;
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nrd=1;
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nrd<=1;
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step=writeret;
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step<=writeret;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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