`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
// Company:
|
// Company:
|
// Engineer: Yihua Liu
|
// Engineer: Yihua Liu
|
//
|
//
|
// Create Date: 2022/06/08 16:50:36
|
// Create Date: 2022/06/08 16:50:36
|
// Design Name:
|
// Design Name:
|
// Module Name: ISR
|
// Module Name: ISR
|
// Project Name: lab_3_b
|
// Project Name: lab_3_b
|
// Target Devices: xczu7eg-ffvf1517-2-i
|
// Target Devices: xczu7eg-ffvf1517-2-i
|
// Tool Versions:
|
// Tool Versions:
|
// Description:
|
// Description:
|
//
|
//
|
// Dependencies:
|
// Dependencies:
|
//
|
//
|
// Revision:
|
// Revision:
|
// Revision 0.01 - File Created
|
// Revision 0.01 - File Created
|
// Additional Comments:
|
// Additional Comments:
|
//
|
//
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
typedef enum logic [3:0] {
|
typedef enum logic [3:0] {
|
INIT,
|
INIT,
|
GUESS,
|
GUESS,
|
MULT_LOAD,
|
MULT_LOAD,
|
MULT_WAIT,
|
MULT_WAIT,
|
COMPARE,
|
COMPARE,
|
CHANGE,
|
CHANGE,
|
CHECK,
|
CHECK,
|
INCRE,
|
INCRE,
|
ENDLOOP,
|
ENDLOOP,
|
DONE
|
DONE
|
} state;
|
} state;
|
|
|
module ISR_FSM(
|
module ISR_FSM(
|
input reset,
|
input reset,
|
input [63:0] value,
|
input [63:0] value,
|
input clock,
|
input clock,
|
input mult_done,
|
input mult_done,
|
input [63:0] mult_result,
|
input [63:0] mult_result,
|
output logic mult_start,
|
output logic mult_start,
|
output logic mult_reset,
|
output logic mult_reset,
|
output logic [63:0] mult_input,
|
output logic [63:0] mult_input,
|
output logic [31:0] result,
|
output logic [31:0] result,
|
output logic done
|
output logic done
|
);
|
);
|
|
|
logic [63:0] value_reg;
|
logic [63:0] value_reg;
|
logic [31:0] result_next, guess, guess_next;
|
logic [31:0] result_next, guess, guess_next;
|
integer i, i_next;
|
integer i, i_next;
|
|
|
state current_state, next_state;
|
state current_state, next_state;
|
|
|
assign mult_input = {32'b0, guess};
|
assign mult_input = {32'b0, guess};
|
assign mult_start = current_state == MULT_LOAD | current_state == MULT_WAIT;
|
assign mult_start = current_state == MULT_LOAD | current_state == MULT_WAIT;
|
assign done = current_state == DONE;
|
assign done = current_state == DONE;
|
assign mult_reset = current_state == INIT | current_state == COMPARE;
|
assign mult_reset = current_state == INIT | current_state == COMPARE;
|
|
|
|
|
always_comb begin
|
always_comb begin
|
guess_next = guess;
|
guess_next = guess;
|
i_next = i;
|
i_next = i;
|
result_next = result;
|
result_next = result;
|
case (current_state)
|
case (current_state)
|
INIT: begin
|
INIT: begin
|
guess_next = 32'h0000_0000;
|
guess_next = 32'h0000_0000;
|
i_next = 31;
|
i_next = 31;
|
result_next = 0;
|
result_next = 0;
|
next_state = GUESS;
|
next_state = GUESS;
|
end
|
end
|
GUESS: begin
|
GUESS: begin
|
guess_next = guess + (32'h0000_0001 << i);
|
guess_next = guess + (32'h0000_0001 << i);
|
next_state = MULT_LOAD;
|
next_state = MULT_LOAD;
|
end
|
end
|
MULT_LOAD: next_state = MULT_WAIT;
|
MULT_LOAD: next_state = MULT_WAIT;
|
MULT_WAIT: next_state = (mult_done) ? COMPARE : MULT_WAIT;
|
MULT_WAIT: next_state = (mult_done) ? COMPARE : MULT_WAIT;
|
COMPARE: next_state = (mult_result > value_reg) ? CHANGE : CHECK;
|
COMPARE: next_state = (mult_result > value_reg) ? CHANGE : CHECK;
|
CHANGE: begin
|
CHANGE: begin
|
guess_next = guess - (32'h0000_0001 << i);
|
guess_next = guess - (32'h0000_0001 << i);
|
next_state = CHECK;
|
next_state = CHECK;
|
end
|
end
|
CHECK: next_state = i ? INCRE : ENDLOOP;
|
CHECK: next_state = i ? INCRE : ENDLOOP;
|
INCRE: begin
|
INCRE: begin
|
i_next = i - 1;
|
i_next = i - 1;
|
next_state = GUESS;
|
next_state = GUESS;
|
end
|
end
|
ENDLOOP: begin
|
ENDLOOP: begin
|
result_next = guess;
|
result_next = guess;
|
next_state = DONE;
|
next_state = DONE;
|
end
|
end
|
DONE: next_state = DONE;
|
DONE: next_state = DONE;
|
default: next_state = INIT;
|
default: next_state = INIT;
|
endcase
|
endcase
|
end
|
end
|
|
|
always_ff @(posedge clock) begin
|
always_ff @(posedge clock) begin
|
if (reset) begin
|
if (reset) begin
|
current_state <= INIT;
|
current_state <= INIT;
|
value_reg <= value;
|
value_reg <= value;
|
result <= 32'b0;
|
result <= 32'b0;
|
i <= 31;
|
i <= 31;
|
guess <= 32'h0000_0000;
|
guess <= 32'h0000_0000;
|
end
|
end
|
else begin
|
else begin
|
current_state <= next_state;
|
current_state <= next_state;
|
value_reg <= value_reg;
|
value_reg <= value_reg;
|
result <= result_next;
|
result <= result_next;
|
i <= i_next;
|
i <= i_next;
|
guess <= guess_next;
|
guess <= guess_next;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
module ISR(
|
module ISR(
|
input reset,
|
input reset,
|
input [63:0] value,
|
input [63:0] value,
|
input clock,
|
input clock,
|
output logic [31:0] result,
|
output logic [31:0] result,
|
output logic done
|
output logic done
|
);
|
);
|
logic mult_start;
|
logic mult_start;
|
logic mult_done;
|
logic mult_done;
|
logic [63:0] mult_result;
|
logic [63:0] mult_result;
|
logic [63:0] mult_input;
|
logic [63:0] mult_input;
|
logic mult_reset;
|
logic mult_reset;
|
|
|
|
|
mult multiplier(
|
mult multiplier(
|
.clock(clock),
|
.clock(clock),
|
.reset(mult_reset),
|
.reset(mult_reset),
|
.mcand(mult_input),
|
.mcand(mult_input),
|
.mplier(mult_input),
|
.mplier(mult_input),
|
.start(mult_start),
|
.start(mult_start),
|
.product(mult_result),
|
.product(mult_result),
|
.done(mult_done)
|
.done(mult_done)
|
);
|
);
|
|
|
ISR_FSM FSM(
|
ISR_FSM FSM(
|
.reset(reset),
|
.reset(reset),
|
.value(value),
|
.value(value),
|
.clock(clock),
|
.clock(clock),
|
.mult_done(mult_done),
|
.mult_done(mult_done),
|
.mult_result(mult_result),
|
.mult_result(mult_result),
|
.mult_start(mult_start),
|
.mult_start(mult_start),
|
.mult_reset(mult_reset),
|
.mult_reset(mult_reset),
|
.mult_input(mult_input),
|
.mult_input(mult_input),
|
.result(result),
|
.result(result),
|
.done(done)
|
.done(done)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
