`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Yihua Liu
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// Engineer: Yihua Liu
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//
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//
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// Create Date: 2022/10/14 01:01:28
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// Create Date: 2022/10/14 01:01:28
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// Design Name:
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// Design Name:
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// Module Name: testbench
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// Module Name: testbench
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// Project Name: lab_3_b
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// Project Name: lab_3_b
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// Target Devices: xczu7eg-ffvf1517-2-i
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// Target Devices: xczu7eg-ffvf1517-2-i
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// Tool Versions:
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// Tool Versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Revision 0.02 - Update Testbench
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// Revision 0.02 - Update Testbench
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module testbench();
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module testbench();
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logic [63:0] test_input;
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logic [63:0] test_input;
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logic clock, reset, quit;
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logic clock, reset, quit;
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logic [31:0] result;
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logic [31:0] result;
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logic done;
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logic done;
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integer i;
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integer i;
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ISR UUT(
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ISR UUT(
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.reset(reset),
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.reset(reset),
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.value(test_input),
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.value(test_input),
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.clock(clock),
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.clock(clock),
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.result(result),
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.result(result),
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.done(done)
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.done(done)
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);
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);
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task compare_correct_result;
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task compare_correct_result;
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input [63:0] value;
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input [63:0] value;
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input [31:0] result;
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input [31:0] result;
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logic [31:0] guess;
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logic [31:0] guess;
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logic [63:0] multi;
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logic [63:0] multi;
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begin
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begin
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// First, calculate the correct result
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// First, calculate the correct result
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guess = 32'h8000_0000;
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guess = 32'h8000_0000;
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for (i = 0; i <= 31; i = i + 1) begin
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for (i = 0; i <= 31; i = i + 1) begin
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guess[31 - i] = 1'b1;
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guess[31 - i] = 1'b1;
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multi = {32'b0, guess};
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multi = {32'b0, guess};
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if ((multi * multi) > value) begin
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if ((multi * multi) > value) begin
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guess[31 - i] = 1'b0;
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guess[31 - i] = 1'b0;
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end
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end
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end
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end
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// Then, compare the result with the correct one
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// Then, compare the result with the correct one
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if (result == guess) begin
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if (result == guess) begin
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end
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end
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else begin
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else begin
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$display("@@@Failed");
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$display("@@@Failed");
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$display("Incorrect at time %4.0f",$time);
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$display("Incorrect at time %4.0f",$time);
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$display("corrent_result = %h result = %h", guess, result);
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$display("corrent_result = %h result = %h", guess, result);
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$finish;
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$finish;
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end
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end
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end
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end
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endtask
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endtask
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always begin
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always begin
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#250;
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#250;
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clock = ~clock;
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clock = ~clock;
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end
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end
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// Some users have had problems just using "@(posedge done)" because their
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// Some users have had problems just using "@(posedge done)" because their
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// "done" signals glitch (even though they are the output of a register). This
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// "done" signals glitch (even though they are the output of a register). This
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// prevents that by making sure "done" is high at the clock edge.
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// prevents that by making sure "done" is high at the clock edge.
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task wait_until_done;
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task wait_until_done;
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forever begin : wait_loop
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forever begin : wait_loop
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@(posedge done);
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@(posedge done);
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@(negedge clock);
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@(negedge clock);
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if (done) disable wait_until_done;
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if (done) disable wait_until_done;
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end
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end
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endtask
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endtask
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initial begin
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initial begin
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$dumpvars;
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$dumpvars;
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$monitor("Time:%4.0f done:%b input:%h result:%h ",$time, done, test_input, result);
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$monitor("Time:%4.0f done:%b input:%h result:%h ",$time, done, test_input, result);
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reset = 0;
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reset = 0;
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clock = 0;
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clock = 0;
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// First some special cases
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// First some special cases
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test_input = 64'h0000_0000_0000_03E9;
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test_input = 64'h0000_0000_0000_03E9;
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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$display("Calculate done!");
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$display("Calculate done!");
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compare_correct_result(test_input, result);
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compare_correct_result(test_input, result);
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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test_input = 64'hFFFF_FFFF_FFFF_FFFF;
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test_input = 64'hFFFF_FFFF_FFFF_FFFF;
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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compare_correct_result(test_input, result);
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compare_correct_result(test_input, result);
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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test_input = 64'h0000_0000_0000_0000;
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test_input = 64'h0000_0000_0000_0000;
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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compare_correct_result(test_input, result);
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compare_correct_result(test_input, result);
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// Then some random tests
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// Then some random tests
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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@(negedge clock);
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@(negedge clock);
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quit = 0;
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quit = 0;
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quit <= #100000 1;
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quit <= #100000 1;
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while (~quit) begin
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while (~quit) begin
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reset = 1;
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reset = 1;
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test_input = {$random, $random};
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test_input = {$random, $random};
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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compare_correct_result(test_input, result);
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compare_correct_result(test_input, result);
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end
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end
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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@(negedge clock);
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@(negedge clock);
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$display("@@@Passed");
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$display("@@@Passed");
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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