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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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typedef enum logic [3:0] {
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module ISR(
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INIT,
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GUESS,
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MULT_LOAD,
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MULT_WAIT,
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COMPARE,
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CHANGE,
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CHECK,
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INCRE,
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ENDLOOP,
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DONE
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} state;
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module ISR_FSM(
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input reset,
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input reset,
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input [63:0] value,
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input [63:0] value,
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input clock,
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input clock,
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input mult_done,
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input [63:0] mult_result,
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output logic mult_start,
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output logic mult_reset,
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output logic [63:0] mult_input,
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output logic [31:0] result,
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output logic [31:0] result,
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output logic done
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output logic done
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);
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);
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logic [63:0] new_value, proposed_solution_square;
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logic [31:0] proposed_solution;
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logic [4:0] i;
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logic start, it_done, flush;
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logic reset_sync;
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logic [63:0] value_reg;
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mult Multiplier (
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logic [31:0] result_next, guess, guess_next;
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.clock(clock),
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integer i, i_next;
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.reset(reset),
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.mcand({32'h00000000, proposed_solution}),
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state current_state, next_state;
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.mplier({32'h00000000, proposed_solution}),
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.start(start),
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assign mult_input = {32'b0, guess};
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.product(proposed_solution_square),
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assign mult_start = current_state == MULT_LOAD | current_state == MULT_WAIT;
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.done(it_done)
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assign done = current_state == DONE;
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);
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assign mult_reset = current_state == INIT | current_state == COMPARE;
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always_comb begin
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always_comb begin
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guess_next = guess;
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// if (reset_async) begin
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i_next = i;
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// done = 0;
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result_next = result;
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// result = 0;
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case (current_state)
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// end
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INIT: begin
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// else begin
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guess_next = 32'h0000_0000;
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// Reduction operator
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i_next = 31;
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// see http://www.asic-world.com/verilog/operators2.html
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result_next = 0;
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// done = ~|i & it_done & ~flush;
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next_state = GUESS;
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// result[i] = (proposed_solution_square <= new_value) & it_done;
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end
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done = ~|i & it_done & ~flush & ~reset_sync;
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GUESS: begin
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result[i] = (proposed_solution_square <= new_value) & it_done & ~reset_sync;
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guess_next = guess + (32'h0000_0001 << i);
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// end
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next_state = MULT_LOAD;
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end
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MULT_LOAD: next_state = MULT_WAIT;
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MULT_WAIT: next_state = (mult_done) ? COMPARE : MULT_WAIT;
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COMPARE: next_state = (mult_result > value_reg) ? CHANGE : CHECK;
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CHANGE: begin
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guess_next = guess - (32'h0000_0001 << i);
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next_state = CHECK;
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end
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CHECK: next_state = i ? INCRE : ENDLOOP;
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INCRE: begin
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i_next = i - 1;
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next_state = GUESS;
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end
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ENDLOOP: begin
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result_next = guess;
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next_state = DONE;
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end
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DONE: next_state = DONE;
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default: next_state = INIT;
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endcase
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end
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end
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always_ff @(posedge clock) begin
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always_ff @(posedge clock or posedge reset) begin
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if (reset) begin
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if (reset) begin
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current_state <= INIT;
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// done <= 0;
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value_reg <= value;
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// result <= 0;
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result <= 32'b0;
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reset_sync <= 1;
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i <= 31;
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start <= 0;
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guess <= 32'h0000_0000;
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flush <= 0;
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i <= 5'b11111;
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proposed_solution <= 32'h80000000;
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new_value <= value;
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end
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end
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else begin
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else begin
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current_state <= next_state;
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reset_sync <= 0;
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value_reg <= value_reg;
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start <= !it_done || !flush;
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result <= result_next;
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flush <= it_done;
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i <= i_next;
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// if (!it_done && flush) begin
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guess <= guess_next;
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// flush <= 0;
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// end
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if (i && it_done && !flush) begin
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// flush <= 1;
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i <= i - 1;
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proposed_solution[i-1] <= 1;
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proposed_solution[i] <= result[i];
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end
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end
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end
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end
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end
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endmodule
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module ISR(
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input reset,
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input [63:0] value,
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input clock,
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output logic [31:0] result,
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output logic done
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);
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logic mult_start;
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logic mult_done;
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logic [63:0] mult_result;
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logic [63:0] mult_input;
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logic mult_reset;
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mult multiplier(
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.clock(clock),
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.reset(mult_reset),
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.mcand(mult_input),
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.mplier(mult_input),
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.start(mult_start),
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.product(mult_result),
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.done(mult_done)
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);
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ISR_FSM FSM(
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.reset(reset),
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.value(value),
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.clock(clock),
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.mult_done(mult_done),
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.mult_result(mult_result),
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.mult_start(mult_start),
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.mult_reset(mult_reset),
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.mult_input(mult_input),
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.result(result),
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.done(done)
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);
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endmodule
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endmodule
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