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`define HALF_CYCLE 1000
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Yihua Liu
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// Engineer: Yihua Liu
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//
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//
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// Create Date: 2022/06/08 16:51:12
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// Create Date: 2022/10/14 01:01:28
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// Design Name:
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// Design Name:
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// Module Name: testbench
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// Module Name: testbench
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// Project Name: lab_3_b
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// Project Name: lab_3_b
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// Target Devices: xczu7eg-ffvf1517-2-i
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// Target Devices: xczu7eg-ffvf1517-2-i
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// Tool Versions:
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// Tool Versions:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Revision 0.02 - Update Testbench
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module testbench();
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module testbench();
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logic [63:0] value;
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logic [63:0] test_input;
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logic clock, reset;
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logic clock, reset, quit;
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logic [31:0] result;
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logic [31:0] result;
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logic done;
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logic done;
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logic [31:0] cres;
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integer i;
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wire correct = (cres===result)|~done|reset;
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ISR UUT(
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integer value_test, j;
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time start_time = $time, finish_time;
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task ISR_test;
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input [63:0] value;
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output [31:0] cres;
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cres = 0;
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for (integer i = 31; i >= 0; i--) begin
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cres[i] = 1;
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if (cres * cres > value)
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cres[i] = 0;
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end
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endtask
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ISR isr(
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.reset(reset),
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.reset(reset),
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.value(value),
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.value(test_input),
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.clock(clock),
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.clock(clock),
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.result(result),
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.result(result),
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.done(done)
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.done(done)
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);
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);
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always @(posedge clock)
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task compare_correct_result;
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#2 if(!correct) begin
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input [63:0] value;
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$display("Incorrect at time %4.0f",$time);
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input [31:0] result;
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$display("cres = %h result = %h",cres,result);
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logic [31:0] guess;
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logic [63:0] multi;
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begin
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// First, calculate the correct result
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guess = 32'h8000_0000;
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for (i = 0; i <= 31; i = i + 1) begin
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guess[31 - i] = 1'b1;
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multi = {32'b0, guess};
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if ((multi * multi) > value) begin
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guess[31 - i] = 1'b0;
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end
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end
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// Then, compare the result with the correct one
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if (result == guess) begin
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end
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else begin
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$display("@@@Failed");
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$display("@@@Failed");
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$display("Incorrect at time %4.0f",$time);
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$display("corrent_result = %h result = %h", guess, result);
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$finish;
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$finish;
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end
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end
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end
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endtask
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always begin
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always begin
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#`HALF_CYCLE;
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#250;
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clock=~clock;
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clock=~clock;
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end
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end
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// Some users have had problems just using "@(posedge done)" because their
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// "done" signals glitch (even though they are the output of a register). This
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// prevents that by making sure "done" is high at the clock edge.
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task wait_until_done;
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task wait_until_done;
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forever begin : wait_loop
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forever begin : wait_loop
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@(posedge done);
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@(posedge done);
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@(negedge clock);
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@(negedge clock);
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if(done) begin
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if (done) disable wait_until_done;
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finish_time = $time;
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$display("Done one calculation of ISR");
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// Calculate the total number of cycles you need to do one calculation of ISR
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// Note that in this way the additional cycles added during simulation will be counted
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// So the displayed value may be 1 to 3 cycles more than 600 cycles
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$display("Number of cycles needed: %d", (finish_time - start_time) / (2 * `HALF_CYCLE));
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start_time = finish_time;
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disable wait_until_done;
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end
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end
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end
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endtask
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endtask
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initial begin
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initial begin
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$monitor("Time:%4.0f done:%b cres:%h result:%h reset:%h",$time,done,cres,result,reset);
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$dumpvars;
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// Test 1
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$monitor("Time:%4.0f done:%b input:%h result:%h ",$time, done, test_input, result);
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value = 0; // square number
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reset = 1;
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clock = 0;
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ISR_test(value, cres);
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#2000;
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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clock = 0;
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@(negedge clock);
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// Test 2
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// First some special cases
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reset = 1;
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test_input = 64'h0000_0000_0000_03E9;
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value = 4; // square number
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ISR_test(value, cres);
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@(negedge clock);
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reset = 0;
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wait_until_done();
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@(negedge clock);
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@(negedge clock);
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// Test 3
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reset = 1;
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reset = 1;
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value = 121; // square number
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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$display("Calculate done!");
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compare_correct_result(test_input, result);
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@(negedge clock);
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@(negedge clock);
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// Test 4
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reset = 1;
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value = 1000000; // square number
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ISR_test(value, cres);
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@(negedge clock);
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reset = 0;
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wait_until_done();
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// Test 5
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reset = 1;
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reset = 1;
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value = 130; // non square number
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test_input = 64'hFFFF_FFFF_FFFF_FFFF;
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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// Test 6
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compare_correct_result(test_input, result);
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@(negedge clock);
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@(negedge clock);
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reset = 1;
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reset = 1;
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value = 2; // non square number (value to be discarded)
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test_input = 64'h0000_0000_0000_0000;
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ISR_test(value, cres);
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@(negedge clock);
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reset = 0;
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@(negedge clock);
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@(negedge clock);
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@(negedge clock);
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reset = 1; // reset is asserted part way through a computation
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value = 3; // non square number (new value to be latched into)
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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compare_correct_result(test_input, result);
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// Then some random tests
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@(negedge clock);
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@(negedge clock);
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@(negedge clock);
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// Test 7
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reset = 1;
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reset = 1;
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value = 64'h7FFF_FFFF_FFFF_FFFF;
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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quit = 0;
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wait_until_done();
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quit <= #100000 1;
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@(negedge clock);
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while (~quit) begin
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value_test = 64'hFFFF_FFFF_FFFF_FFFF;
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// Short loops
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for (j = 0; j < 100; j++) begin
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reset = 1;
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reset = 1;
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value = value_test;
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test_input = {$random, $random};
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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reset = 0;
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wait_until_done();
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wait_until_done();
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value_test = value_test - 64'h0000_0000_7FFF_FFFF;
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compare_correct_result(test_input, result);
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end
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end
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// Random testing
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@(negedge clock);
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for (j = 0; j < 1000; j++) begin
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reset = 1;
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reset = 1;
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value = {$random, $random};
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ISR_test(value, cres);
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@(negedge clock);
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@(negedge clock);
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reset = 0;
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wait_until_done();
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end
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$display("@@@Passed");
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$display("@@@Passed");
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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