URL
https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 4 |
| Line 1... |
Line 1... |
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
// Company:
|
// Company:
|
// Engineer: Sebastien Riou
|
// Engineer: Sebastien Riou
|
//
|
//
|
// Create Date: 23:57:02 08/31/2010
|
// Create Date: 23:57:02 08/31/2010
|
| Line 18... |
Line 19... |
// Additional Comments:
|
// Additional Comments:
|
//
|
//
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
module Counter(
|
module Counter(
|
output reg [WIDTH-1:0] counter,
|
output reg [WIDTH-1:0] counter,
|
output earlyMatch,
|
output wire earlyMatch,
|
output reg match,
|
output reg match,
|
output dividedClk,
|
output wire dividedClk,
|
input [DIVIDER_WIDTH-1:0] divider, // clock divide factor
|
input wire [DIVIDER_WIDTH-1:0] divider, // clock divide factor
|
input [WIDTH-1:0] compare,
|
input wire [WIDTH-1:0] compare,
|
input inc,
|
input wire inc,
|
input clear,
|
input wire clear,
|
input [WIDTH_INIT-1:0] initVal,
|
input wire [WIDTH_INIT-1:0] initVal,
|
input clk,
|
input wire clk,
|
input nReset
|
input wire nReset
|
);
|
);
|
|
|
//parameters to override
|
//parameters to override
|
parameter DIVIDER_WIDTH = 16;
|
parameter DIVIDER_WIDTH = 16;
|
parameter WIDTH = 8;
|
parameter WIDTH = 8;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.