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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Sebastien Riou
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// Engineer: Sebastien Riou
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//
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//
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// Create Date: 23:57:02 08/31/2010
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// Create Date: 23:57:02 08/31/2010
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg dataOutReadyFlag, //new data available
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output reg dataOutReadyFlag, //new data available
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg run, //rx is definitely started, one of the three flag will be set
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output reg run, //rx is definitely started, one of the three flag will be set
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output startBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
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input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input ackFlags,
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input wire ackFlags,
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input serialIn,
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input wire serialIn,
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input clk,
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input wire clk,
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input nReset,
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input wire nReset,
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//to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
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//to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
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output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
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output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
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output reg bitClocksCounterInc,
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output reg bitClocksCounterInc,
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output reg bitClocksCounterClear,
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output reg bitClocksCounterClear,
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output bitClocksCounterInitVal,
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output wire bitClocksCounterInitVal,
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input bitClocksCounterEarlyMatch,
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input wire bitClocksCounterEarlyMatch,
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input bitClocksCounterMatch
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input wire bitClocksCounterMatch
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);
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);
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//parameters to override
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//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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//invert the polarity of the output or not
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//invert the polarity of the output or not
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