| Line 12... |
Line 12... |
-- This will be work in process or replaced whatever
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-- This will be work in process or replaced whatever
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-- project file is needed to control other modules.
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-- project file is needed to control other modules.
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--
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--
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-- *************************************************************
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-- *************************************************************
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-- Distributed under the GNU Lesser General Public License. *
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-- Distributed under the GNU Lesser General Public License. *
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-- This can be obtained from “www.gnu.org”. *
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-- This can be obtained from www.gnu.org. *
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-- *************************************************************
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-- *************************************************************
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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| Line 48... |
Line 48... |
-- u1101 : out std_logic;
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-- u1101 : out std_logic;
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-- u801 : out std_logic;
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-- u801 : out std_logic;
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-- u701 : out std_logic;
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-- u701 : out std_logic;
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u601 : out std_logic;
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u601 : out std_logic;
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rst_pin : in std_logic;
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rst_pin : in std_logic;
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irq_pin : in std_logic;
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-- irq_pin : in std_logic;
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nmi_pin : in std_logic;
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-- nmi_pin : in std_logic;
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RX_pin : in std_logic;
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RX_pin : in std_logic;
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-- PG_pin : in std_logic;
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-- PG_pin : in std_logic;
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TX_pin : out std_logic;
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TX_pin : out std_logic;
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Pwr_on_pin : out std_logic
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Pwr_on_pin : out std_logic
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);
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);
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| Line 136... |
Line 136... |
signal add : unsigned(15 downto 0);
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signal add : unsigned(15 downto 0);
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signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
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signal proc_rd_dat, rom_dat, ram_dat, data_wr : unsigned(7 downto 0);
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signal rx_dat : unsigned(7 downto 0);
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signal rx_dat : unsigned(7 downto 0);
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signal proc_write : std_logic;
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signal proc_write : std_logic;
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signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
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signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic;
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-- signal cycle_mark : std_logic
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signal rst_bar : std_logic;
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signal rst_bar : std_logic;
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signal ram_write : std_logic;
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signal ram_write : std_logic;
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--signal clk : std_logic;
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--signal clk_pin : std_logic;
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signal counter : unsigned(3 downto 0);
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signal counter : unsigned(3 downto 0);
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signal nmi_pin, irq_pin : std_logic;
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-- I/O ports
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-- I/O ports
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constant led_port : unsigned (15 downto 0) := x"4007";
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constant led_port : unsigned (15 downto 0) := x"4007";
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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constant Kirq : unsigned (15 downto 0) := X"4002"; --interrpt testing only
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constant Knmi : unsigned (15 downto 0) := x"4003";
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begin
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begin
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|
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U1 : P65C02 port map(
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U1 : P65C02 port map(
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reset => rst_pin,
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reset => rst_pin,
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Clock => clk_pin,
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Clock => clk_pin,
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| Line 207... |
Line 209... |
-- Reset => rst_bar,
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-- Reset => rst_bar,
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-- Clock => clk_pin,
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-- Clock => clk_pin,
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-- WE => ram_write,
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-- WE => ram_write,
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-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
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-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
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-- Data => std_logic_vector(data_wr),
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-- Data => std_logic_vector(data_wr),
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-- unsigned(Q) => ram_dat, ClockEn => one);
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-- unsigned(Q) => ram_dat
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-- ClockEn => one);
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one <= '1';
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one <= '1';
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rst_bar <= not rst_pin;
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rst_bar <= not rst_pin;
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one <= '1';
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ram_write <= proc_write and not address(15) and not address(14);
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--one <= '1';
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--u601 <= cycle_mark;
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--u601 <= cycle_mark;
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mux_add : process(rst_pin, clk_pin)
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mux_add : process(rst_pin, clk_pin)
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| Line 225... |
Line 231... |
elsif rising_edge(clk_pin) then
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elsif rising_edge(clk_pin) then
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add <= address;
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add <= address;
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end if;
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end if;
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end process;
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end process;
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ram_address : process (proc_write, address(15 downto 14))
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--ram_address : process (proc_write, address(15 downto 14))
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begin
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--begin
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if proc_write = '1' and address(15 downto 14) = "00" then
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-- if proc_write = '1' and address(15 downto 14) = "00" then
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ram_write <= '1';
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-- ram_write <= '1';
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else
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-- else
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ram_write <= '0';
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-- ram_write <= '0';
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end if;
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-- end if;
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end process;
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--end process;
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-- ===================================================================
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-- ===================================================================
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| Line 273... |
Line 279... |
end if;
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end if;
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end process;
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end process;
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relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
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--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
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begin
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--begin
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if rst_pin = '0' then
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--if rst_pin = '0' then
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Pwr_on_pin <= '0';
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-- Pwr_on_pin <= '0';
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elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
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-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
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Pwr_on_pin <= data_wr(7);
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-- Pwr_on_pin <= data_wr(7);
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end if;
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--end if;
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end process;
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--end process;
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--irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
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--begin
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--if rst_pin = '0' then
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-- irq_pin <= '1';
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-- elsif rising_edge(clk_pin) then
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-- if address = Kirq and proc_write = '1' then
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-- irq_pin <= data_wr(0); --set and hold bit 0
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-- end if;
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--end if;
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--end process;
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--nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
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--begin
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--if rst_pin = '0' then
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-- nmi_pin <= '1';
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-- elsif rising_edge(clk_pin) then
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--
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-- if address = Knmi and proc_write = '1' then
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-- nmi_pin <= data_wr(0); --set and hold bit 0
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-- end if;
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--end if;
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--end process;
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end structure;
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end structure;
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No newline at end of file
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No newline at end of file
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