| Line 3... |
Line 3... |
--
|
--
|
-- Copyright Ian Chapman October 28 2010
|
-- Copyright Ian Chapman October 28 2010
|
--
|
--
|
-- This file is part of the Lattice 6502 project
|
-- This file is part of the Lattice 6502 project
|
-- It is used to compile with Linux ghdl and ispLeaver.
|
-- It is used to compile with Linux ghdl and ispLeaver.
|
--
|
-- email author@kool.kor
|
|
-- author EQU ichapman
|
|
-- kool EQU videotron
|
|
-- kor EQU ca
|
--
|
--
|
-- To do
|
-- To do
|
-- Detailed test of all instructions.
|
-- Detailed test of all instructions.
|
--
|
--
|
-- *************************************************************
|
-- *************************************************************
|
| Line 55... |
Line 58... |
------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
-- TO Do
|
-- TO Do
|
-- 1 DONE Update all address modes of cmp, cpx and cpy per #mode
|
-- 1 DONE Update all address modes of cmp, cpx and cpy per #mode
|
-- 2 DONE Add rol, ror, asl, lsr, per inc and dec
|
-- 2 DONE Add rol, ror, asl, lsr, per inc and dec
|
-- 3 DONE Correct flags in all modes of item 2
|
-- 3 DONE Correct flags in all modes of item 2
|
-- 4 Update the stack instructions, I've it pushing up not down.
|
-- 4 DONE Update the stack instructions, I've it pushing up not down.
|
-- 5 Continue testing
|
-- 5 Continue testing
|
-- 6 DONE Get a kernel up to test each and every instruction
|
-- 6 DONE Get a kernel up to test each and every instruction
|
-- 7 Test all instructions
|
-- 7 Test all instructions
|
-- 7 Add the 65C02 stuff. I think the most needed is phx, phy, plx
|
-- 7 Add the 65C02 stuff. I think the most needed is phx, phy, plx
|
-- and ply are the most useful.
|
-- and ply are the most useful.
|
------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
-- Revision history
|
-- Revision history
|
|
-- Dec 3, 2010
|
|
-- Interrupts BRK, IRQ and NMI checked out seem okay.
|
|
-- Fixed stack to push down pull up.
|
|
-- addressing (zero,x) corrected.
|
|
-- CLV error corrected.
|
|
-- rol, ror, asl and lsr shift instructions checked and fixed.
|
|
-- Nov 17, 2010
|
|
-- Corrected BRK, IRQ, NMI and RTI due to error in status byte.
|
-- Nov 4, 2010
|
-- Nov 4, 2010
|
-- Rationalized all flavours of cmp, cpy and cpx.
|
-- Rationalized all flavours of cmp, cpy and cpx.
|
-- Changed jsr to combine out_dat1 and out_dat2 into out_dat.
|
-- Changed jsr to combine out_dat1 and out_dat2 into out_dat.
|
-- Changed wr_ctr to wr_fg.
|
-- Changed wr_ctr to wr_fg.
|
-- This saved 43 slices, 69% of slices are used.
|
-- This saved 43 slices, 69% of slices are used.
|
| Line 109... |
Line 120... |
signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff, wr_fg : std_logic;
|
signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff, wr_fg : std_logic;
|
signal cycle_ctr, add_fg : unsigned(3 downto 0);
|
signal cycle_ctr, add_fg : unsigned(3 downto 0);
|
signal flags_fg : unsigned(1 downto 0);
|
signal flags_fg : unsigned(1 downto 0);
|
|
|
|
|
signal reset_fg, irq_fg, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic;
|
signal reset_fg, irq_fg, nmi_ff1, nmi_ff2, nmi_req, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic;
|
signal pc_dec_fg, dat2pc_fg : std_logic;
|
signal pc_dec_fg, dat2pc_fg : std_logic;
|
-- End of signal declarations
|
-- End of signal declarations
|
|
|
begin --architecture
|
begin --architecture
|
-- =======================================================
|
-- =======================================================
|
| Line 127... |
Line 138... |
elsif rising_edge(clock) then
|
elsif rising_edge(clock) then
|
dat_in2 <= dat_in1;
|
dat_in2 <= dat_in1;
|
dat_in1 <= data_rd;
|
dat_in1 <= data_rd;
|
|
|
if cycle_ctr = x"0" then
|
if cycle_ctr = x"0" then
|
if irq = '0' or nmi = '0' or (reset = '1' and reset_fg = '0') then
|
-- if (i_fg = '0' and (irq = '0' or nmi_req = '0')) or (reset = '1' and reset_fg = '0') then
|
|
if (i_fg = '0' and irq = '0') or nmi_req = '0' or (reset = '1' and reset_fg = '0') then
|
Instruction_in <= x"00";
|
Instruction_in <= x"00";
|
else
|
else
|
Instruction_in <= data_rd;
|
Instruction_in <= data_rd;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 146... |
Line 158... |
elsif rising_edge(clock) then
|
elsif rising_edge(clock) then
|
if dat2pc_fg = '1' then
|
if dat2pc_fg = '1' then
|
reg_pc(15 downto 8) <= data_rd;
|
reg_pc(15 downto 8) <= data_rd;
|
reg_pc(7 downto 0) <= dat_in1;
|
reg_pc(7 downto 0) <= dat_in1;
|
|
|
elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then
|
-- elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then
|
|
elsif cycle_ctr = X"0" or pc_inc_fg = '1' then
|
reg_pc <= reg_pc + x"0001";
|
reg_pc <= reg_pc + x"0001";
|
|
|
elsif pc_dec_fg = '1' then
|
elsif pc_dec_fg = '1' then
|
reg_pc <= reg_pc - x"0001";
|
reg_pc <= reg_pc - x"0001";
|
|
|
| Line 161... |
Line 174... |
reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1);
|
reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process Prog_ptr;
|
end process Prog_ptr;
|
|
|
addressing:process (clock, reset, reg_PC, add_fg)
|
addressing:process (reset, proc_write, data_rd, dat_in1, dat_in2, reg_x, reg_y, reg_sp, add_hold, reg_PC, add_fg)
|
begin
|
begin
|
|
|
if reset = '0' then
|
if reset = '0' then
|
address <= reg_pc;
|
address <= reg_pc;
|
else
|
else
|
Case add_fg is
|
Case add_fg is
|
when x"0" =>
|
when x"0" =>
|
| Line 204... |
Line 218... |
address <= data_rd & dat_in1 + reg_x;
|
address <= data_rd & dat_in1 + reg_x;
|
else
|
else
|
address <= dat_in1 & dat_in2 + reg_x;
|
address <= dat_in1 & dat_in2 + reg_x;
|
end if;
|
end if;
|
when x"6" => --Absolute, y
|
when x"6" => --Absolute, y
|
address <= (data_rd & dat_in1) + reg_y;
|
-- address <= (data_rd & dat_in1) + reg_y;
|
|
|
if proc_write = '0' then
|
if proc_write = '0' then
|
address <= data_rd & dat_in1 + reg_y;
|
address <= data_rd & dat_in1 + reg_y;
|
else
|
else
|
address <= dat_in1 & dat_in2 + reg_y;
|
address <= dat_in1 & dat_in2 + reg_y;
|
| Line 228... |
Line 242... |
address(7 downto 0) <= dat_in1 + "1";
|
address(7 downto 0) <= dat_in1 + "1";
|
address(15 downto 8) <= x"00";
|
address(15 downto 8) <= x"00";
|
when x"D" => --(zero,x)
|
when x"D" => --(zero,x)
|
address(7 downto 0) <= dat_in1 + reg_x + "1";
|
address(7 downto 0) <= dat_in1 + reg_x + "1";
|
address(15 downto 8) <= x"00";
|
address(15 downto 8) <= x"00";
|
when x"F" => --Hold address steady for INC etc
|
when x"F" => --Hold addre nmi_ff1 <= '0';ss steady for INC etc
|
address <= add_hold;
|
address <= add_hold;
|
when others =>
|
when others =>
|
address <= reg_pc;
|
address <= reg_pc;
|
end case;
|
end case;
|
end if;
|
end if;
|
| Line 250... |
Line 264... |
memory_proc_write:process(clock, reset, wr_fg)
|
memory_proc_write:process(clock, reset, wr_fg)
|
begin
|
begin
|
if reset = '0' then
|
if reset = '0' then
|
data_wr <= (others => '0');
|
data_wr <= (others => '0');
|
proc_write <= '0';
|
proc_write <= '0';
|
|
|
elsif rising_edge(clock) then
|
elsif rising_edge(clock) then
|
proc_write <= wr_fg;
|
proc_write <= wr_fg;
|
if wr_fg = '1' then
|
-- if wr_fg = '1' then
|
data_wr <= dat_out;
|
data_wr <= dat_out;
|
end if;
|
-- end if;
|
end if;
|
end if;
|
end process memory_proc_write;
|
end process memory_proc_write;
|
|
|
instruction_decode:process (clock, reset, irq, nmi)
|
instruction_decode:process (clock, reset, irq, nmi)
|
begin
|
begin
|
| Line 272... |
Line 287... |
flags_fg <= (others => '0');
|
flags_fg <= (others => '0');
|
wr_fg <= '0';
|
wr_fg <= '0';
|
reg_a <= (others => '0');
|
reg_a <= (others => '0');
|
reg_x <= (others => '0');
|
reg_x <= (others => '0');
|
reg_y <= (others => '0');
|
reg_y <= (others => '0');
|
reg_s <= (others => '0');
|
reg_sp <= (others => '1');
|
reg_sp <= (others => '0');
|
|
n_fg <= '0';
|
n_fg <= '0';
|
v_fg <= '0';
|
v_fg <= '0';
|
b_fg <= '0';
|
b_fg <= '0';
|
d_fg <= '0';
|
d_fg <= '0';
|
i_fg <= '0';
|
i_fg <= '1';
|
z_fg <= '0';
|
z_fg <= '0';
|
reset_fg <= '0';
|
reset_fg <= '0';
|
start_fg <= '0';
|
start_fg <= '0';
|
v_ff <= '0';
|
v_ff <= '0';
|
|
nmi_ff1 <= '1';
|
|
nmi_ff2 <= '1';
|
|
nmi_req <= '1';
|
nmi_fg <= '0';
|
nmi_fg <= '0';
|
irq_fg <= '0';
|
irq_fg <= '0';
|
dat_out <= (others => '0');
|
dat_out <= (others => '0');
|
|
|
elsif rising_edge(clock) then
|
elsif rising_edge(clock) then
|
reset_fg <= reset;
|
reset_fg <= reset;
|
|
-- This is to generate a nmi_req from neg transition on nmi input
|
|
nmi_ff1 <= nmi;
|
|
nmi_ff2 <= nmi_ff1;
|
|
if nmi_fg = '0' and nmi_ff2 = '1' and nmi = '0' then
|
|
nmi_req <= '0';
|
|
end if;
|
|
|
-- This section is to get started
|
-- This section is to get started
|
if reset = '1' and reset_fg = '0' then
|
if reset = '1' and reset_fg = '0' then
|
start_fg <= '1';
|
start_fg <= '1';
|
wr_fg <= '0';
|
wr_fg <= '0';
|
add_fg <= x"8"; --get start up vectors FFFC FFFD
|
add_fg <= x"8"; --get start up vectors FFFC FFFD
|
cycle_ctr <= x"5"; --Jump into cycle 5 add_fg <= x'8'
|
cycle_ctr <= x"7"; --Jump into cycle 7 add_fg <= x'8'
|
-- end if;
|
-- end if;
|
else
|
else
|
|
|
|
|
case cycle_ctr is --cycle counter case
|
case cycle_ctr is --cycle counter case
|
| Line 323... |
Line 346... |
flags_fg <= "00";
|
flags_fg <= "00";
|
end if;
|
end if;
|
|
|
if irq = '0' and i_fg = '0' then
|
if irq = '0' and i_fg = '0' then
|
irq_fg <= '1';
|
irq_fg <= '1';
|
b_fg <= '0';
|
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
elsif nmi = '0' and i_fg = '0' then
|
elsif nmi_req = '0' then
|
nmi_fg <= '1';
|
nmi_fg <= '1';
|
b_fg <= '0';
|
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
else
|
else
|
|
|
case data_rd is
|
case data_rd is
|
| Line 343... |
Line 364... |
dat_out <= reg_a(7 downto 0);
|
dat_out <= reg_a(7 downto 0);
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"08" => --PHP 1st part status onto stack
|
when x"08" => --PHP 1st part status onto stack
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1'; --php needs extra cycle to propagate flags
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"68" => --PLA 1st part Pull Accumulator from Stack
|
when x"68" => --PLA 1st part Pull Accumulator from Stack
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"28" => --PLP 1st part pull old status from stack
|
when x"28" => --PLP 1st part pull old status from stack
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
pc_dec_fg <= '1';
|
pc_dec_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"18" => --CLC clear carry
|
when x"18" => --CLC clear carry
|
reg_a(8) <= '0';
|
reg_a(8) <= '0';
|
-- pc_dec_fg <= '1';
|
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"38" => --SEC set carry
|
when x"38" => --SEC set carry
|
reg_a(8) <= '1';
|
reg_a(8) <= '1';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
| Line 388... |
Line 408... |
flags_fg <= "01";
|
flags_fg <= "01";
|
dat_out <= reg_a(7 downto 0);
|
dat_out <= reg_a(7 downto 0);
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
when x"B8" => --CLV clear overflow flag
|
when x"B8" => --CLV clear overflow flag
|
v_fg <= '0';
|
v_fg <= '0';
|
pc_dec_fg <= '1';
|
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
when x"C8" => --INY increment Y reg
|
when x"C8" => --INY increment Y reg
|
reg_y <= reg_y + x"1";
|
reg_y <= reg_y + x"1";
|
flags_fg <= "01";
|
flags_fg <= "01";
|
dat_out <= reg_y + x"1";
|
dat_out <= reg_y + x"1";
|
| Line 630... |
Line 649... |
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"35" => --AND zero,X 1st part
|
when x"35" => --AND zero,X 1st part
|
add_fg <= x"2";
|
add_fg <= x"2";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"36" => --ROL zero,X 1st part
|
when x"36" => --ROL zero,X 1st part
|
add_fg <= x"1";
|
add_fg <= x"2";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"45" => --EOR zero 1st part
|
when x"45" => --EOR zero 1st part
|
add_fg <= x"1";
|
add_fg <= x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"46" => --LSR zero 1st part
|
when x"46" => --LSR zero 1st part
|
| Line 804... |
Line 823... |
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
-- ............................................................................
|
-- ............................................................................
|
-- ==============================================================================
|
-- ==============================================================================
|
|
|
|
|
when x"4C" => --JMP abs first part
|
when x"4C" => --JMP abs 1st part
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"6C" => --JMP indirect first part
|
when x"6C" => --JMP indirect 1st part
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"20" => --JSR abs first part
|
when x"20" => --JSR abs 1st part
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"60" => --RTS first part
|
when x"60" => --RTS 1st part
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
add_fg <= x"7";
|
add_fg <= x"7";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"40" => --RTI 1st part pull old status from stack
|
when x"40" => --RTI 1st part pull old status from stack
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
add_fg <= x"7";
|
add_fg <= x"7";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"00" => --Break first part cyc 0
|
when x"00" => --Break 1st part cyc 0
|
if irq_fg = '0' then --Start up, irq and nmi also use
|
pc_dec_fg <= '1'; --Start up, irq and nmi also use.
|
b_fg <= '1'; --this set of logic.
|
cycle_ctr <= cycle_ctr + x"1"; --this set of logic.
|
else
|
|
b_fg <= '0';
|
|
end if;
|
|
pc_dec_fg <= '1';
|
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
end case; --Cycle 0
|
end case; --Cycle 0
|
| Line 1230... |
Line 1244... |
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"BD" => --LDA, x abs 2nd part.
|
when x"BD" => --LDA, x abs 2nd part.
|
add_fg <= x"5";
|
add_fg <= x"5";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"B9" => --LDA, Y abs 2nd part.
|
when x"B9" => --LDA, Y abs 2nd part.
|
|
|
|
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
|
|
when x"2D" => --AND abs 2nd part.
|
when x"2D" => --AND abs 2nd part.
|
add_fg <= x"4";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"3D" => --AND, x abs 2nd part.
|
when x"3D" => --AND, x abs 2nd part.
|
| Line 1388... |
Line 1405... |
wr_fg <= '1';
|
wr_fg <= '1';
|
dat_out <= reg_pc(15 downto 8);
|
dat_out <= reg_pc(15 downto 8);
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"60" => --RTS second part
|
when x"60" => --RTS second part
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"40" => --RTI second part pull old status from stack
|
when x"40" => --RTI second part pull old status from stack
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"00" => --Break second part cyc 1
|
when x"00" => --Break 2nd part cyc 1
|
dat2pc_fg <= '0';
|
if irq_fg = '0' and nmi_fg = '0' then --Start up, irq and nmi also use
|
wr_fg <= '1'; --put dat_out onto stack
|
pc_dec_fg <= '0'; --this set of logic.
|
dat_out <= reg_pc(15 downto 8);
|
end if;
|
add_fg <= x"7";
|
|
pc_dec_fg <= '0';
|
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
end case; --Cycle 1
|
end case; --Cycle 1
|
| Line 1417... |
Line 1432... |
-- ====================================================================================
|
-- ====================================================================================
|
|
|
when x"48" => --PHA 3rd part accumulator onto stack
|
when x"48" => --PHA 3rd part accumulator onto stack
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
add_fg <= x"0";
|
add_fg <= x"0";
|
reg_sp <= reg_sp + "1";
|
reg_sp <= reg_sp - "1"; --neg
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"08" => --PHP 3rd part Status reg onto stack
|
when x"08" => --PHP 3rd part Status reg onto stack
|
wr_fg <= '0';
|
wr_fg <= '0';
|
add_fg <= x"7";
|
add_fg <= x"7";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
| Line 1700... |
Line 1715... |
wr_fg <= '1';
|
wr_fg <= '1';
|
flags_fg <= "01";
|
flags_fg <= "01";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"F6" => --INC zero,X 3rd part
|
when x"F6" => --INC zero,X 3rd part
|
dat_out <= data_rd + x"01";
|
dat_out <= data_rd + x"01";
|
|
|
wr_fg <= '1';
|
wr_fg <= '1';
|
flags_fg <= "01";
|
flags_fg <= "01";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"66" => --ROR zero 3rd part
|
when x"66" => --ROR zero 3rd part
|
|
dat_out(6 downto 0) <= data_rd(7 downto 1);
|
|
dat_out(7) <= reg_a(8);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
dat_out <= reg_a(8) & data_rd(7 downto 1);
|
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"76" => --ROR zero,X 3rd part
|
when x"76" => --ROR zero,X 3rd part
|
|
dat_out(6 downto 0) <= data_rd(7 downto 1);
|
|
dat_out(7) <= reg_a(8);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
dat_out <= reg_a(8) & data_rd(7 downto 1);
|
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"26" => --ROL zero 3rd part
|
when x"26" => --ROL zero 3rd part
|
dat_out(7 downto 1) <= data_rd(6 downto 0);
|
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8);
|
dat_out(0) <= reg_a(8);
|
reg_a(8) <= data_rd(7);
|
flags_fg <= "01";
|
flags_fg <= "01";
|
wr_fg <= '1';
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"36" => --ROL zero,X 3rd part
|
when x"36" => --ROL zero,X 3rd part
|
dat_out(7 downto 1) <= data_rd(6 downto 0);
|
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8);
|
dat_out(0) <= reg_a(8);
|
reg_a(8) <= data_rd(7);
|
flags_fg <= "01";
|
flags_fg <= "01";
|
wr_fg <= '1';
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"46" => --LSR zero 3rd part
|
when x"46" => --LSR zero 3rd part
|
dat_out <= '0' & reg_a(7 downto 1);
|
dat_out <= '0' & data_rd(7 downto 1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"56" => --LSR zero,X 3rd part
|
when x"56" => --LSR zero,X 3rd part
|
dat_out <= '0' & reg_a(7 downto 1);
|
dat_out <= '0' & data_rd(7 downto 1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"06" => --ASL zero 3rd part
|
when x"06" => --ASL zero 3rd part
|
reg_a(8) <= data_rd(7);
|
reg_a(8) <= data_rd(7);
|
dat_out <= data_rd(6 downto 0) & '0';
|
dat_out <= data_rd(6 downto 0) & '0';
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"16" => --ASL zero,X 3rd part
|
when x"16" => --ASL zero,X 3rd part
|
reg_a(8) <= data_rd(7);
|
reg_a(8) <= data_rd(7);
|
dat_out <= data_rd(6 downto 0) & data_rd(0);
|
dat_out <= data_rd(6 downto 0) & '0';
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1'; wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
-- =============================================================================================
|
-- =============================================================================================
|
when x"A1" => --LDA (zero,x) 3rd part proto
|
when x"A1" => --LDA (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"B1" => --LDA (zero),y 3rd part proto
|
when x"B1" => --LDA (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"21" => --AMD (zero,x) 3rd part proto
|
when x"21" => --AMD (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"31" => --AND (zero),y 3rd part proto
|
when x"31" => --AND (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"41" => --EOR (zero,x) 3rd part proto
|
when x"41" => --EOR (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"51" => --EOR (zero),y 3rd part proto
|
when x"51" => --EOR (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"01" => --OR (zero,x) 3rd part proto
|
when x"01" => --OR (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"11" => --OR (zero),y 3rd part proto
|
when x"11" => --OR (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"61" => --ADC (zero,x) 3rd part proto
|
when x"61" => --ADC (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"71" => --ADC (zero),y 3rd part proto
|
when x"71" => --ADC (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"E1" => --SBC (zero,x) 3rd part proto
|
when x"E1" => --SBC (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"F1" => --SBC (zero),y 3rd part proto
|
when x"F1" => --SBC (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when x"C1" => --CMP (zero,x) 3rd part proto
|
when x"C1" => --CMP (zero,x) 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"4";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"D1" => --CMP (zero),y 3rd part proto
|
when x"D1" => --CMP (zero),y 3rd part proto
|
add_fg <= x"6";
|
add_fg <= x"6";
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
| Line 2020... |
Line 2034... |
dat2pc_fg <= '0';
|
dat2pc_fg <= '0';
|
add_fg <= x"7";
|
add_fg <= x"7";
|
wr_fg <= '1';
|
wr_fg <= '1';
|
dat_out <= reg_pc(7 downto 0);
|
dat_out <= reg_pc(7 downto 0);
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"60" => --RTS third part
|
when x"60" => --RTS 3rd part
|
dat2pc_fg <= '1';
|
dat2pc_fg <= '1';
|
add_fg <= x"0";
|
add_fg <= x"0";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"40" => --RTI 3rd part pull old status from stack
|
when x"40" => --RTI 3rd part pull old status from stack
|
pc_dec_fg <= '0'; --Get 1st PC byte
|
pc_dec_fg <= '0'; --Get 1st PC byte
|
| Line 2033... |
Line 2047... |
b_fg <= data_rd(4);
|
b_fg <= data_rd(4);
|
d_fg <= data_rd(3);
|
d_fg <= data_rd(3);
|
i_fg <= data_rd(2);
|
i_fg <= data_rd(2);
|
z_fg <= data_rd(1);
|
z_fg <= data_rd(1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
reg_sp <= reg_sp - "1";
|
reg_sp <= reg_sp + "1"; --plus
|
dat2pc_fg <= '1';
|
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"00" => --Break third part cyc 2
|
when x"00" => --Break 3rd part cyc 2
|
dat_out <= reg_pc(7 downto 0); --put dat_out onto stack set up dat_out
|
if irq_fg = '0' and nmi_fg = '0' then --Start up, irq and nmi also use
|
reg_sp <= reg_sp + "1";
|
b_fg <= '1'; --this set of logic.
|
|
else
|
|
b_fg <= '0';
|
|
end if;
|
|
wr_fg <= '1'; --put dat_out onto stack
|
|
dat_out <= reg_pc(15 downto 8);
|
|
add_fg <= x"7";
|
|
pc_dec_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
end case; --Cycle 2
|
end case; --Cycle 2
|
| Line 2089... |
Line 2109... |
|
|
|
|
when x"08" => --PHP 4th part accumulator onto stack
|
when x"08" => --PHP 4th part accumulator onto stack
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
add_fg <= x"0";
|
add_fg <= x"0";
|
reg_sp <= reg_sp + "1";
|
reg_sp <= reg_sp - "1"; --neg
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"48" => --PHA 4th part accumulator onto stack
|
when x"48" => --PHA 4th part accumulator onto stack
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
| Line 2104... |
Line 2124... |
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
when x"28" => --PLP 4th part Pull Status from Stack
|
when x"28" => --PLP 4th part Pull Status from Stack
|
n_fg <= data_rd(7);
|
n_fg <= data_rd(7);
|
v_fg <= data_rd(6);
|
v_fg <= data_rd(6);
|
-- b_fg <= data_rd(4);
|
b_fg <= data_rd(4);
|
d_fg <= data_rd(3);
|
d_fg <= data_rd(3);
|
i_fg <= data_rd(2);
|
i_fg <= data_rd(2);
|
z_fg <= data_rd(1);
|
z_fg <= data_rd(1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
| Line 2396... |
Line 2416... |
wr_fg <= '1';
|
wr_fg <= '1';
|
flags_fg <= "01";
|
flags_fg <= "01";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"2E" => --ROL abs 4th part.
|
when x"2E" => --ROL abs 4th part.
|
dat_out(7 downto 1) <= data_rd(6 downto 0);
|
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8);
|
dat_out(0) <= reg_a(8);
|
reg_a(8) <= data_rd(7);
|
flags_fg <= "01";
|
flags_fg <= "01";
|
wr_fg <= '1';
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"3E" => --ROL, x abs 4th part.
|
when x"3E" => --ROL, x abs 4th part.
|
dat_out(7 downto 1) <= data_rd(6 downto 0);
|
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8);
|
dat_out(0) <= reg_a(8);
|
reg_a(8) <= data_rd(7);
|
flags_fg <= "01";
|
flags_fg <= "01";
|
wr_fg <= '1';
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"6E" => --ROR abs 4th part.
|
when x"6E" => --ROR abs 4th part.
|
|
dat_out(6 downto 0) <= data_rd(7 downto 1);
|
|
dat_out(7) <= reg_a(8);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
dat_out <= reg_a(8) & data_rd(7 downto 1);
|
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"7E" => --ROR, x abs 4th part.
|
when x"7E" => --ROR, x abs 4th part.
|
|
dat_out(6 downto 0) <= data_rd(7 downto 1);
|
|
dat_out(7) <= reg_a(8);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
dat_out <= reg_a(8) & data_rd(7 downto 1);
|
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"4E" => --LSR abs 4th part.
|
when x"4E" => --LSR abs 4th part.
|
dat_out <= '0' & reg_a(7 downto 1);
|
dat_out <= '0' & data_rd(7 downto 1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"5E" => --LSR, x abs 4th part.
|
when x"5E" => --LSR, x abs 4th part.
|
dat_out <= '0' & reg_a(7 downto 1);
|
dat_out <= '0' & data_rd(7 downto 1);
|
reg_a(8) <= data_rd(0);
|
reg_a(8) <= data_rd(0);
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
|
wr_fg <= '1';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
when x"0E" => --ASL abs 4th part.
|
when x"0E" => --ASL abs 4th part.
|
reg_a(8) <= data_rd(7);
|
reg_a(8) <= data_rd(7);
|
dat_out <= data_rd(6 downto 0) & data_rd(0);
|
dat_out <= data_rd(6 downto 0) & '0';
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
cycle_ctr <= cycle_ctr + x"1";
|
wr_fg <= '1';
|
|
cycle_ctr <= cycle_ctr + "1";
|
when x"1E" => --ASL, x abs 4th part.
|
when x"1E" => --ASL, x abs 4th part.
|
reg_a(8) <= data_rd(7);
|
reg_a(8) <= data_rd(7);
|
dat_out <= data_rd(6 downto 0) & data_rd(0);
|
dat_out <= data_rd(6 downto 0) & '0';
|
wr_fg <= '1';
|
|
flags_fg <= "01";
|
flags_fg <= "01";
|
cycle_ctr <= cycle_ctr + x"1";
|
wr_fg <= '1';
|
|
cycle_ctr <= cycle_ctr + "1";
|
-- ............................................................................
|
-- ............................................................................
|
-- ==============================================================================
|
-- ==============================================================================
|
when x"A1" => --LDA (zero,x) 4th part proto
|
when x"A1" => --LDA (zero,x) 4th part proto
|
add_fg <= x"0";
|
add_fg <= x"0";
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
| Line 2535... |
Line 2557... |
dat2pc_fg <= '1';
|
dat2pc_fg <= '1';
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"20" => --JSR indirect 4th part
|
when x"20" => --JSR indirect 4th part
|
wr_fg <= '0';
|
wr_fg <= '0';
|
reg_sp <= reg_sp + "1";
|
reg_sp <= reg_sp - "1"; --neg
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"60" => --RTS fourth part
|
when x"60" => --RTS fourth part
|
dat2pc_fg <= '0';
|
dat2pc_fg <= '0';
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"40" => --RTI forth part
|
when x"40" => --RTI forth part
|
-- reg_sp <= reg_sp - "1";
|
|
add_fg <= x"7"; --Get 2nd PC byte
|
add_fg <= x"7"; --Get 2nd PC byte
|
dat2pc_fg <= '0';
|
dat2pc_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"00" => --Break forth extra part cyc 3
|
when x"00" => --Break 4th part cyc 3
|
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8);
|
dat_out <= reg_pc(7 downto 0); --put dat_out onto stack set up dat_out
|
reg_sp <= reg_sp + "1";
|
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
--------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
| Line 2929... |
Line 2949... |
dat2pc_fg <= '0';
|
dat2pc_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"20" => --JSR 5th part
|
when x"20" => --JSR 5th part
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
add_fg <= x"0";
|
add_fg <= x"0";
|
reg_sp <= reg_sp + "1";
|
reg_sp <= reg_sp - "1"; --neg
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"60" => --RTS fifth part
|
when x"60" => --RTS fifth part
|
dat2pc_fg <= '0';
|
dat2pc_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"40" => --RTI fifth part
|
when x"40" => --RTI fifth part
|
-- reg_sp <= reg_sp + "1";
|
-- reg_sp <= reg_sp + "1";
|
add_fg <= x"0";
|
add_fg <= x"0";
|
-- dat2pc_fg <= '0';
|
dat2pc_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"00" => --Break fifth part cyc 4
|
when x"00" => --Break 5th extra part cyc 4
|
wr_fg <= '0';
|
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8);
|
reg_sp <= reg_sp + "1";
|
reg_sp <= reg_sp - "1"; --neg
|
if nmi_fg = '0' then
|
|
add_fg <= x"9"; --Complete stacking start getting vector
|
|
else
|
|
add_fg <= x"A";
|
|
end if;
|
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
end case; --Cycle 4
|
end case; --Cycle 4
|
-- end if;
|
-- end if;
|
| Line 3053... |
Line 3067... |
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
when x"1E" => --ASL, x 6th part.
|
when x"1E" => --ASL, x 6th part.
|
add_fg <= x"0";
|
add_fg <= x"0";
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
-- ........................................................................................
|
-- ........................................................................................
|
|
|
when x"6C" => --JMP indirect 6th part
|
when x"6C" => --JMP indirect 6th part
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"60" => --RTS 6th part
|
when x"60" => --RTS 6th part
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"40" => --RTI sixth part
|
when x"40" => --RTI sixth part
|
cycle_ctr <= cycle_ctr + x"1";
|
|
pc_inc_fg <= '1';
|
pc_inc_fg <= '1';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when x"20" => --JSR 6th part
|
when x"20" => --JSR 6th part
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"00" => --Break 6th part cyc 5
|
when x"00" => --Break 6th part cyc 5
|
add_fg <= x"B";
|
wr_fg <= '0';
|
irq_fg <= '0';
|
reg_sp <= reg_sp - "1"; --neg
|
nmi_fg <= '0';
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
|
when others =>
|
when others =>
|
|
|
cycle_ctr <= cycle_ctr + x"1";
|
cycle_ctr <= cycle_ctr + x"1";
|
end case; --Cycle 5
|
end case; --Cycle 5
|
| Line 3125... |
Line 3138... |
when x"40" => --RTI 7th part
|
when x"40" => --RTI 7th part
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"00" => --Break 7th part cyc 6
|
when x"00" => --Break 7th part cyc 6
|
dat2pc_fg <= '1';
|
wr_fg <= '0';
|
add_fg <= x"0";
|
reg_sp <= reg_sp - "1"; --neg
|
cycle_ctr <= cycle_ctr + "1";
|
if nmi_fg = '0' then
|
|
add_fg <= x"9"; --Complete stacking start getting vector
|
|
else
|
|
add_fg <= x"A";
|
|
end if;
|
|
cycle_ctr <= cycle_ctr + x"1";
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
--get_inst_fg <= '0';
|
--get_inst_fg <= '0';
|
|
|
| Line 3147... |
Line 3165... |
|
|
when x"40" => --RTI 8th cyc
|
when x"40" => --RTI 8th cyc
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
when x"00" => --Break 8th part cyc 7
|
when x"00" => --Break 8th part cyc 7
|
if start_fg = '0' then --When starting don't mess with this
|
add_fg <= x"B";
|
i_fg <= '1'; --Break irq and start use this logic.
|
irq_fg <= '0';
|
|
nmi_fg <= '0';
|
|
nmi_req <= '1';
|
|
if irq_fg = '1' then
|
|
i_fg <= '1';
|
end if;
|
end if;
|
pc_inc_fg <= '1';
|
|
start_fg <= '0';
|
|
dat2pc_fg <= '0';
|
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= x"0";
|
cycle_ctr <= x"0";
|
|
|
end case; --Cycle 7
|
end case; --Cycle 7
|
-- Cycle 7
|
-- Cycle 7
|
when x"8" =>
|
when x"8" =>
|
case Instruction_in is
|
case Instruction_in is
|
|
when x"00" => --Break 9th part cyc 8
|
when x"00" => --Break 10th part cyc 8
|
dat2pc_fg <= '1';
|
pc_inc_fg <= '0';
|
add_fg <= x"0";
|
cycle_ctr <= x"0";
|
cycle_ctr <= cycle_ctr + "1";
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= x"0";
|
pc_inc_fg <= '0';
|
|
|
|
end case; --Cycle 8
|
end case; --Cycle 8
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- Cycle 9
|
-- Cycle 9
|
when x"9" =>
|
when x"9" =>
|
case Instruction_in is
|
case Instruction_in is
|
|
when x"00" => --Break 10th part cyc 9
|
when others =>
|
pc_inc_fg <= '1';
|
|
start_fg <= '0';
|
|
dat2pc_fg <= '0';
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
pc_inc_fg <= '0';
|
|
|
|
|
when others =>
|
|
cycle_ctr <= x"0";
|
end case; --Cycle 9
|
end case; --Cycle 9
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- Cycle A
|
-- Cycle A
|
|
|
when x"A" =>
|
when x"A" =>
|
case Instruction_in is
|
case Instruction_in is
|
|
when x"00" => --Break 11th part cyc 10
|
|
pc_inc_fg <= '0';
|
|
cycle_ctr <= x"0";
|
|
|
when others =>
|
when others =>
|
cycle_ctr <= cycle_ctr + "1";
|
cycle_ctr <= cycle_ctr + "1";
|
pc_inc_fg <= '0';
|
pc_inc_fg <= '0';
|
|
|
