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------------------------------------------------------------------
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------------------------------------------------------------------
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-- 6502 Top module.
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-- 6502 Top module.
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--
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--
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-- Copyright Ian Chapman October 28 2010
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-- Copyright Ian Chapman October 28 2010
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--
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-- email author@kool.kor
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-- author EQU ichapman
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-- kool EQU videotron
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-- kor EQU ca
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-- ******************************************************
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-- Dec 12 2010
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-- RAM increased to 2k 0 to $7ff for bigger test code
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-- sta irq and sta nmi trigger interrupts
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-- ******************************************************
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-- This file is part of the Lattice 6502 project
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-- This file is part of the Lattice 6502 project
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-- It is used to compile with ispLeaver not Linux ghdl.
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-- It is used to compile with ispLeaver not Linux ghdl.
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-- It is the address mapping and connecting the other modules.
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-- It is the address mapping and connecting the other modules.
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-- It is replaced by Processor.vhd when running ispLeaver.
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-- It is replaced by Processor.vhd when running ispLeaver.
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--
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--
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-- To do
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-- To do
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-- This will be work in process or replaced whatever
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-- This will be work in process or replaced whatever
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-- project file is needed to control other modules.
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-- project file is needed to control other modules.
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--
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--
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-- *************************************************************
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-- *************************************************************
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>
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-- along with this program. If not, see <http://www.gnu.org/licenses/>
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--
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--
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-- Processor.vhd
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-- Processor.vhd
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Revision history
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-- Nov 411, 2010
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-- To facilitate testing of NMI and IRQ.
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-- changed from I/O pins to signals
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-- IRQ and NMI address decoded so as to initiated the inerupt from
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------------------------------------------------------------------
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library IEEE; --Use standard IEEE libs as recommended by Tristan.
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library IEEE; --Use standard IEEE libs as recommended by Tristan.
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity Processor is
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entity Processor is
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-- u1101 : out std_logic;
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-- u1101 : out std_logic;
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-- u801 : out std_logic;
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-- u801 : out std_logic;
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-- u701 : out std_logic;
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-- u701 : out std_logic;
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u601 : out std_logic;
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u601 : out std_logic;
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rst_pin : in std_logic;
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rst_pin : in std_logic;
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irq_pin : in std_logic;
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-- irq_pin : in std_logic; --disabled to test interrupts on fpga
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nmi_pin : in std_logic;
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-- nmi_pin : in std_logic;
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RX_pin : in std_logic;
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RX_pin : in std_logic;
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-- PG_pin : in std_logic;
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-- PG_pin : in std_logic;
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TX_pin : out std_logic;
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TX_pin : out std_logic;
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Pwr_on_pin : out std_logic
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Pwr_on_pin : out std_logic
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);
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);
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port (
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port (
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Clock: in std_logic;
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Clock: in std_logic;
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ClockEn: in std_logic;
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ClockEn: in std_logic;
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Reset: in std_logic;
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Reset: in std_logic;
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WE: in std_logic;
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WE: in std_logic;
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Address: in std_logic_vector(9 downto 0);
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Address: in std_logic_vector(10 downto 0);
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Data: in std_logic_vector(7 downto 0);
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Data: in std_logic_vector(7 downto 0);
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Q: out std_logic_vector(7 downto 0));
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Q: out std_logic_vector(7 downto 0));
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end component;
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end component;
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--component ghdl_rom
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--component ghdl_rom
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signal clk : std_logic;
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signal clk : std_logic;
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--signal clk_pin : std_logic;
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--signal clk_pin : std_logic;
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signal counter : unsigned(3 downto 0);
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signal counter : unsigned(3 downto 0);
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signal ram_write : std_logic;
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signal ram_write : std_logic;
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signal irq_pin, nmi_pin : std_logic;
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-- I/O ports
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-- I/O ports
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constant led_port : unsigned (15 downto 0) := x"4007";
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--constant led_port : unsigned (15 downto 0) := x"4007";
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constant irq : unsigned (15 downto 0) := X"4002";
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constant nmi : unsigned (15 downto 0) := x"4003";
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting
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begin
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begin
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R4 : Lattice_ram port map(
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R4 : Lattice_ram port map(
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Reset => rst_bar,
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Reset => rst_bar,
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Clock => clk_pin,
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Clock => clk_pin,
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WE => ram_write,
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WE => ram_write,
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address(9 downto 0) => std_logic_vector(Address(9 downto 0)),
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address(10 downto 0) => std_logic_vector(Address(10 downto 0)),
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Data => std_logic_vector(data_wr),
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Data => std_logic_vector(data_wr),
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unsigned(Q) => ram_dat, ClockEn => one);
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unsigned(Q) => ram_dat, ClockEn => one);
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-- address(9 downto 0) => (Address(9 downto 0)),
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-- address(9 downto 0) => (Address(9 downto 0)),
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-- Data => (data_wr),
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-- Data => (data_wr),
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-- (Q) => ram_dat, ClockEn => one);
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-- (Q) => ram_dat, ClockEn => one);
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one <= '1';
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one <= '1';
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rst_bar <= not rst_pin;
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rst_bar <= not rst_pin;
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one <= '1';
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one <= '1';
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--ram_write <= proc_write and not address(15) and not address(14) and not address(13) and not address(12) and not address(11) and not address(10);
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--ram_write <= proc_write and not address(15) and not address(14);
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--irq_pin <= '1'; --only used to test interrupts on fpga
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--nmi_pin <= '1';
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--u601 <= cycle_mark;
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--u601 <= cycle_mark;
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mux_add : process(rst_pin, clk_pin)
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mux_add : process(rst_pin, clk_pin)
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csw_usart <= '1';
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csw_usart <= '1';
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else
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else
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csw_usart <= '0';
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csw_usart <= '0';
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end if;
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end if;
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end process;
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end process;
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-- Only uded to test interrupts in the fpga
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-- These two processe let the SW fire NMI and IRG
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-- with a sta instruction.
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irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
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begin
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if rst_pin = '0' then
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irq_pin <= '1';
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elsif rising_edge(clk_pin) then
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if address = irq and proc_write = '1' then
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irq_pin <= data_wr(0); --set and hold bit 0
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end if;
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end if;
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end process;
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nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin)
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relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
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begin
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begin
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if rst_pin = '0' then
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if rst_pin = '0' then
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Pwr_on_pin <= '0';
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nmi_pin <= '1';
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elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
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elsif rising_edge(clk_pin) then
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Pwr_on_pin <= data_wr(7);
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if address = nmi and proc_write = '1' then
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nmi_pin <= data_wr(0); --set and hold bit 0
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end if;
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end if;
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end if;
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end process;
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end process;
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--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin)
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--begin
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--if rst_pin = '0' then
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-- Pwr_on_pin <= '0';
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-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then
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-- Pwr_on_pin <= data_wr(7);
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--end if;
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--end process;
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end structure;
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end structure;
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No newline at end of file
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No newline at end of file
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