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https://opencores.org/ocsvn/lfsr_randgen/lfsr_randgen/trunk
[/] [lfsr_randgen/] [trunk/] [lfsr.vhd] - Diff between revs 2 and 3
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Rev 3 |
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Line 49... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library work;
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library work;
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use work.lfsr_pkg.ALL;
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use work.lfsr_pkg.ALL;
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entity lfsr is
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entity lfsr is
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generic (width : integer := 32);
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generic (width : integer := 4);
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port (clk : in std_logic;
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port (clk : in std_logic;
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set_seed : in std_logic;
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set_seed : in std_logic;
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out_enable : in std_logic;
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seed : in std_logic_vector(width-1 downto 0);
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seed : in std_logic_vector(width-1 downto 0);
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rand_out : out std_logic_vector(width-1 downto 0)
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rand_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end lfsr;
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end lfsr;
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architecture Behavioral of lfsr is
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architecture Behavioral of lfsr is
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begin
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begin
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process(clk,set_seed,out_enable,seed)
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process(clk)
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variable rand_temp : std_logic_vector (width-1 downto 0):=(0 => '1',others => '0');
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variable rand_temp : std_logic_vector (width-1 downto 0):=(0 => '1',others => '0');
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variable temp : std_logic := '0';
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variable temp : std_logic := '0';
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begin
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begin
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if(rising_edge(clk)) then
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if(set_seed = '1') then
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if(set_seed = '1') then
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rand_temp := seed;
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rand_temp := seed;
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elsif(rising_edge(clk)) then
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end if;
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temp := xor_gates(rand_temp);
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temp := xor_gates(rand_temp);
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rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
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rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
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rand_temp(0) := temp;
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rand_temp(0) := temp;
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end if;
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if(out_enable ='1') then
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rand_out <= rand_temp;
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else
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rand_out <= (others => '0');
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end if;
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end if;
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rand_out <= rand_temp;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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