| Line 59... |
Line 59... |
pc : t_address;
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pc : t_address;
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pc_prev : t_address;
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pc_prev : t_address;
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next_pc : t_address;
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next_pc : t_address;
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pc_z : t_addr_array;
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pc_z : t_addr_array;
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ps : t_cpu_state;
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ps : t_cpu_state;
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jump_condition : std_logic;
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rel_jump_target : t_address;
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bram_we : std_logic;
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bram_we : std_logic;
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bram_wr_addr : t_bram_addr;
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bram_wr_addr : t_bram_addr;
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bram_wr_data_p0 : t_byte;
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bram_wr_data_p0 : t_byte;
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sfr_we : std_logic;
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sfr_we : std_logic;
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sfr_wr : t_byte;
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sfr_wr : t_byte;
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sfr_addr : t_byte;
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sfr_addr : t_byte;
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delayed_acc_log : boolean;
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delayed_acc_value : t_byte;
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-- Observed cycle count for all executed opcodes.
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-- Observed cycle count for all executed opcodes.
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cycles : t_cycle_count;
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cycles : t_cycle_count;
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last_opcode : std_logic_vector(7 downto 0);
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last_opcode : std_logic_vector(7 downto 0);
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opcode : std_logic_vector(7 downto 0);
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opcode : std_logic_vector(7 downto 0);
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| Line 132... |
Line 136... |
file l_file : TEXT;
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file l_file : TEXT;
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file con_file : TEXT) is
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file con_file : TEXT) is
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variable bram_wr_addr : unsigned(7 downto 0);
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variable bram_wr_addr : unsigned(7 downto 0);
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variable opc : natural;
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variable opc : natural;
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variable num_cycles : natural;
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variable num_cycles : natural;
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variable jump_logged : boolean := false;
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begin
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begin
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jump_logged := false;
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-- Update the opcode observed cycle counters.
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-- Update the opcode observed cycle counters.
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-- For every opcode, we count the cycles from its decode_0 state to the
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-- For every opcode, we count the cycles from its decode_0 state to the
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-- next fetch_1 state. To this we have to add 2 (one each for states
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-- next fetch_1 state. To this we have to add 2 (one each for states
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-- decode_0 and fetch_1) and we have the cycle count.
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-- decode_0 and fetch_1) and we have the cycle count.
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-- we store the min and the max because of conditional jumps.
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-- we store the min and the max because of conditional jumps.
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| Line 177... |
Line 184... |
if info.sfr_we = '1' then
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if info.sfr_we = '1' then
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print(l_file, "("& hstr(info.pc)& ") SFR["&
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print(l_file, "("& hstr(info.pc)& ") SFR["&
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hstr(info.sfr_addr)& "] = "& hstr(info.sfr_wr));
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hstr(info.sfr_addr)& "] = "& hstr(info.sfr_wr));
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end if;
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end if;
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-- Log jumps
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-- FIXME remove internal state dependency
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--if info.ps = jrb_bit_3 and info.jump_condition='1' then
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-- Catch attempts to jump to addresses out of the ROM bounds -- assume
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-- mirroring is not expected to be useful in this case.
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-- Note it remains possible to just run into uninitialized ROM areas
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-- or out of ROM bounds, we're not checking any of that.
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--assert info.next_pc < info.rom_size
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--report "Jump to unmapped code address "& hstr(info.next_pc)&
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-- "h at "& hstr(info.pc)& "h. Simulation stopped."
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--severity failure;
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-- print(l_file, "("& hstr(info.pc)& ") PC = "&
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-- hstr(info.rel_jump_target) );
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--end if;
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-- Log ACC updates.
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-- Log ACC updates.
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-- Note we exclude the 'intermediate update' of ACC in DA instruction.
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-- Note we exclude the 'intermediate update' of ACC in DA instruction, and
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-- we have to deal with another tricky special case:
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-- the JBC instruction needs the ACC change log delayed so that it appears
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-- after the PC change log -- a nasty hack meant to avoid a nastier hack
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-- in the SW simulator logging code.
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if (info.load_acc='1' and info.ps/=alu_daa_0) then
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if (info.load_acc='1' and info.ps/=alu_daa_0) then
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if info.a_reg_prev /= info.acc_input then
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if info.a_reg_prev /= info.acc_input then
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if info.ps = jrb_bit_2 then -- this state is only used in JBC
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info.delayed_acc_log <= true;
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info.delayed_acc_value <= info.acc_input;
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else
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print(l_file, "("& hstr(info.pc)& ") A = "&
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print(l_file, "("& hstr(info.pc)& ") A = "&
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hstr(info.acc_input) );
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hstr(info.acc_input) );
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end if;
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end if;
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end if;
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info.a_reg_prev <= info.acc_input;
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info.a_reg_prev <= info.acc_input;
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end if;
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end if;
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-- Log XRAM writes
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-- Log XRAM writes
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if (info.xdata_we='1') then
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if (info.xdata_we='1') then
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| Line 264... |
Line 296... |
"h at "& hstr(info.pc)& "h. Simulation stopped."
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"h at "& hstr(info.pc)& "h. Simulation stopped."
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severity failure;
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severity failure;
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print(l_file, "("& hstr(info.pc)& ") PC = "&
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print(l_file, "("& hstr(info.pc)& ") PC = "&
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hstr(info.next_pc) );
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hstr(info.next_pc) );
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jump_logged := true;
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end if;
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-- If this instruction needs the ACC change log delayed, display it now
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-- but only if the PC change has been already logged.
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-- This only happens in instructions that jump AND can modify ACC: JBC.
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-- The PSW change, if any, is delayed too, see below.
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if info.delayed_acc_log and jump_logged then
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print(l_file, "("& hstr(info.pc)& ") A = "&
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hstr(info.delayed_acc_value) );
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info.delayed_acc_log <= false;
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end if;
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end if;
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-- Log PSW implicit updates: first, whenever the PSW is updated, save the PC
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-- Log PSW implicit updates: first, whenever the PSW is updated, save the PC
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-- for later reference...
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-- for later reference...
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if (info.update_psw_flags(0)='1' or info.load_acc='1') then
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if (info.update_psw_flags(0)='1' or info.load_acc='1') then
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| Line 275... |
Line 318... |
end if;
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end if;
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-- ...then, when the PSW change is actually detected, log it along with the
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-- ...then, when the PSW change is actually detected, log it along with the
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-- PC value we saved before.
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-- PC value we saved before.
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-- The PSW changes late in the instruction cycle and we need this trick to
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-- The PSW changes late in the instruction cycle and we need this trick to
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-- keep the logs ordered.
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-- keep the logs ordered.
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if (info.psw) /= (info.psw_prev) then
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-- Note that if the ACC log is delayed, the PSW log is delayed too!
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if (info.psw) /= (info.psw_prev) and not info.delayed_acc_log then
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print(l_file, "("& hstr(info.psw_update_addr)& ") PSW = "& hstr(info.psw) );
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print(l_file, "("& hstr(info.psw_update_addr)& ") PSW = "& hstr(info.psw) );
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info.psw_prev <= info.psw;
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info.psw_prev <= info.psw;
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end if;
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end if;
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-- Stop the simulation if we find an unconditional, one-instruction endless
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-- Stop the simulation if we find an unconditional, one-instruction endless
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| Line 334... |
Line 378... |
init_signal_spy(mcu& "/cpu/SP_reg", iname&".sp", 0);
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init_signal_spy(mcu& "/cpu/SP_reg", iname&".sp", 0);
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init_signal_spy(mcu& "/cpu/"&"psw", iname&".psw", 0);
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init_signal_spy(mcu& "/cpu/"&"psw", iname&".psw", 0);
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init_signal_spy(mcu& "/cpu/"&"update_psw_flags",iname&".update_psw_flags(0)", 0);
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init_signal_spy(mcu& "/cpu/"&"update_psw_flags",iname&".update_psw_flags(0)", 0);
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init_signal_spy(mcu& "/cpu/"&"code_addr", iname&".code_addr", 0);
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init_signal_spy(mcu& "/cpu/"&"code_addr", iname&".code_addr", 0);
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init_signal_spy(mcu& "/cpu/"&"ps", iname&".ps", 0);
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init_signal_spy(mcu& "/cpu/"&"ps", iname&".ps", 0);
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init_signal_spy(mcu& "/cpu/"&"jump_condition", iname&".jump_condition", 0);
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init_signal_spy(mcu& "/cpu/"&"rel_jump_target", iname&".rel_jump_target", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_we", iname&".bram_we", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_we", iname&".bram_we", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_addr_p0", iname&".bram_wr_addr", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_addr_p0", iname&".bram_wr_addr", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_wr_data_p0", iname&".bram_wr_data_p0", 0);
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init_signal_spy(mcu& "/cpu/"&"bram_wr_data_p0", iname&".bram_wr_data_p0", 0);
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init_signal_spy(mcu& "/cpu/"&"next_pc", iname&".next_pc", 0);
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init_signal_spy(mcu& "/cpu/"&"next_pc", iname&".next_pc", 0);
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init_signal_spy(mcu& "/cpu/"&"sfr_we", iname&".sfr_we", 0);
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init_signal_spy(mcu& "/cpu/"&"sfr_we", iname&".sfr_we", 0);
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| Line 368... |
Line 414... |
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-- Initialize the observed cycle counting logic...
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-- Initialize the observed cycle counting logic...
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info.cycles <= (others => (999,0,0));
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info.cycles <= (others => (999,0,0));
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info.cycle_count <= 0;
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info.cycle_count <= 0;
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info.last_opcode <= "UUUUUUUU";
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info.last_opcode <= "UUUUUUUU";
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info.delayed_acc_log <= false;
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-- ...and we're ready to start monitoring the system
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-- ...and we're ready to start monitoring the system
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while done='0' loop
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while done='0' loop
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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if reset='1' then
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if reset='1' then
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