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[/] [light8080/] [trunk/] [tools/] [ihex2vlog/] [ihex2vlog.exe] - Diff between revs 65 and 68

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Rev 65 Rev 68 
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Usage: ihex2vlog [-a/s/m/4/16]  
ERROR: incorrect usage of program.
 
optional parameters:
 
     -a  generate initialization vectors for generic Verilog
 
Usage: ihex2vlog [-a/s/m/4/16]  
                code with specified address bus width. value should be
 
optional parameters:
 
                in the range 8 to 16.
 
     -a  generate initialization vectors for generic Verilog
 
                this is the default option with width = 16
 
                code with specified address bus width. value should be
 
     -s  set size of generic verilog memory size.
 
                in the range 8 to 16.
 
                value should be in the range 256 to 65536.
 
                this is the default option with width = 16
 
                default value is 2** (address width defined above).
 
     -s  set size of generic verilog memory size.
 
     -m   set module name for generic verilog memory.
 
                value should be in the range 256 to 65536.
 
                default value is "ram_image".
 
                default value is 2** (address width defined above).
 
     -4         generate initialization vectors for Xilinx RAMB4.
 
     -m   set module name for generic verilog memory.
 
     -16        generate initialization vectors for Xilinx RAMB16.
 
                default value is "ram_image".
 
     -4         generate initialization vectors for Xilinx RAMB4.
 
Example: ihex2vlog test.ihx ram_image.v
 
     -16        generate initialization vectors for Xilinx RAMB16.
 
%d
 
ERROR: Address width value error (%d)
 
Example: ihex2vlog test.ihx ram_image.v
 
%d
 
%d
 
ERROR: Address width value error (%d)
 
ERROR: Memory size value error (%d)
 
%d
 
ERROR: Memory size value error (%d)
 
ERROR: Unsupported option "%s"
 
HEX memory top address %d
 
ERROR: Unsupported option "%s"
 
ERROR: Can't read '%s'!
 
Writing output file to: %s
 
HEX memory top address %d
 
wtERROR: Can't write '%s'!
 
ERROR: Can't read '%s'!
 
HEX file requires %d RAM blocks
 
Writing output file to: %s
 
// RAM image for input code file: %s
 
wtERROR: Can't write '%s'!
 
// enable memory blocks
 
HEX file requires %d RAM blocks
 
`ifdef EN_ALL_BLOCKS
 
// RAM image for input code file: %s
 
`define EN_BLOCK%d     1
 
// enable memory blocks
 
`else
 
`ifdef EN_ALL_BLOCKS
 
`define EN_BLOCK%d     1
 
`define EN_BLOCK%d     1
 
`endif
 
`else
 
`define EN_BLOCK%d     1
 
// block %d
 
`endif
 
defparam mem%d.INIT_%X%X = 256'h%x%x;
 
Generate generic Verilog RAM code.
 
// block %d
 
//-----------------------------------------------------------------------------
 
defparam mem%d.INIT_%X%X = 256'h%x%x;
 
//
 
Generate generic Verilog RAM code.
 
// RAM image for input code file: %s
 
//-----------------------------------------------------------------------------
 
//
 
//
 
//-----------------------------------------------------------------------------
 
// RAM image for input code file: %s
 
module %s
 
//
 
(
 
//-----------------------------------------------------------------------------
 
       clk, addr,
 
module %s
 
       we, din, dout
 
(
 
);
 
       clk, addr,
 
//-----------------------------------------------------------------------------
 
       we, din, dout
 
input           clk;
 
);
 
input   [%d:0]  addr;
 
//-----------------------------------------------------------------------------
 
input           we;
 
input           clk;
 
input   [7:0]   din;
 
input   [%d:0]  addr;
 
output  [7:0]   dout;
 
input           we;
 
//-----------------------------------------------------------------------------
 
input   [7:0]   din;
 
reg [7:0] dout;
 
output  [7:0]   dout;
 
reg [7:0] ram [%d:0];
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
 
reg [7:0] dout;
 
initial
 
reg [7:0] ram [%d:0];
 
begin
 
//-----------------------------------------------------------------------------
 
    ram[%d] = 8'h%x%x;
 
initial
 
end
 
begin
 
    ram[%d] = 8'h%x%x;
 
//-----------------------------------------------------------------------------
 
end
 
always @(posedge clk)
 
begin
 
//-----------------------------------------------------------------------------
 
    if (we)
 
always @(posedge clk)
 
        ram[addr] <= din;
 
begin
 
    dout <= ram[addr];
 
    if (we)
 
end
 
    begin
 
        ram[addr] <= din;
 
endmodule
 
        dout <= din;
 
//-----------------------------------------------------------------------------
 
    end
 
%02x%04x%02x%02x%02xCan't load a file without the filename.  '?' for help
 
    else
 
rCan't open file '%s' for reading.
 
        dout <= ram[addr];
 
Loaded %d bytes between: %04X to %04X
 
end
 
   Error: '%s', line: %d
 
   Must specify address range and filename
 
endmodule
 
%x%x%s   Invalid addresses or filename,
 
//-----------------------------------------------------------------------------
 
    usage: S begin_addr end_addr filename
 
%02x%04x%02x%02x%02xCan't load a file without the filename.  '?' for help
 
    the addresses must be hexidecimal format
 
rCan't open file '%s' for reading.
 
   Begin address must be less than end address.
 
Loaded %d bytes between: %04X to %04X
 
w   Can't open '%s' for writing.
 
   Error: '%s', line: %d
 
Memory %04X to %04X written to '%s'
 
   Must specify address range and filename
 
:%02X%04X00%02X%02X
 
%x%x%s   Invalid addresses or filename,
 
:00000001FF
 
    usage: S begin_addr end_addr filename
 
 
 
    the addresses must be hexidecimal format
 
 
 
   Begin address must be less than end address.
 
 
 
w   Can't open '%s' for writing.
 
 
 
Memory %04X to %04X written to '%s'
 
 
 
:%02X%04X00%02X%02X
 
 
 
:00000001FF
 
 
 
 

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