| Line 39... |
Line 39... |
#<alu_dst> := <register> | DO
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#<alu_dst> := <register> | DO
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#<alu_op> := add|adc|sub|sbb| and|orl|not|xrl| rla|rra|rlca|rrca| aaa|
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#<alu_op> := add|adc|sub|sbb| and|orl|not|xrl| rla|rra|rlca|rrca| aaa|
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# t1|rst|daa|cpc|sec|psw
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# t1|rst|daa|cpc|sec|psw
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#<flag list> := <flag> [, <flag> ...]
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#<flag list> := <flag> [, <flag> ...]
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#<flag> := #decode|#di|#ei|#io|#auxcy|#clrt1|#halt|#end|#ret|#rd|#wr|#setacy
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#<flag> := #decode|#di|#ei|#io|#auxcy|#clrt1|#halt|#end|#ret|#rd|#wr|#setacy
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# #ld_al|#ld_addr|#fp_c|#fp_r|#fp_rc (*2)
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# #ld_al|#ld_addr|#fp_c|#fp_r|#fp_rc|#clr_cy_ac (*2)
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#
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#
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# *1 Labels appear alone by themselves in a line
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# *1 Labels appear alone by themselves in a line
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# *2 There are some restrictions on the flags that can be used together
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# *2 There are some restrictions on the flags that can be used together
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# *3 Registers are specified by IR field
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# *3 Registers are specified by IR field
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#
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#
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| Line 91... |
Line 91... |
# #ld_al : Load AL register with register bank output as read by operation 1.
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# #ld_al : Load AL register with register bank output as read by operation 1.
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# (used in memory and io access).
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# (used in memory and io access).
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# #ld_addr : Load address register (H byte = register bank output as read by
|
# #ld_addr : Load address register (H byte = register bank output as read by
|
# operation 1, L byte = AL).
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# operation 1, L byte = AL).
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# Activate vma signal for 1st cycle.
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# Activate vma signal for 1st cycle.
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# #clr_acy : Instruction clears CY and AC flags. Use with #fp_rc.
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# --- PSW update flags: use only one of these
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# --- PSW update flags: use only one of these
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# #fp_r : This instruction updates all PSW flags except for C.
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# #fp_r : This instruction updates all PSW flags except for C.
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# #fp_c : This instruction updates only the C flag in the PSW.
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# #fp_c : This instruction updates only the C flag in the PSW.
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# #fp_rc : This instruction updates all the flags in the PSW.
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# #fp_rc : This instruction updates all the flags in the PSW.
|
################################################################################
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################################################################################
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| Line 564... |
Line 565... |
substr($uinst->{field1},22,2) = '10';
|
substr($uinst->{field1},22,2) = '10';
|
}
|
}
|
if($uinst->{flags} =~ /#fp_rc/){
|
if($uinst->{flags} =~ /#fp_rc/){
|
substr($uinst->{field1},22,2) = '11';
|
substr($uinst->{field1},22,2) = '11';
|
}
|
}
|
|
if($uinst->{flags} =~ /#clr_acy/){
|
|
substr($uinst->{field1},17,1) = '1';
|
|
}
|
|
|
}
|
}
|
|
|
sub process_flags {
|
sub process_flags {
|
|
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| Line 659... |
Line 662... |
$uinst->{flags} = $uinst->{flags}." #fp_r";
|
$uinst->{flags} = $uinst->{flags}." #fp_r";
|
}
|
}
|
if($flag_str =~ /#fp_rc/){
|
if($flag_str =~ /#fp_rc/){
|
$uinst->{flags} = $uinst->{flags}." #fp_rc";
|
$uinst->{flags} = $uinst->{flags}." #fp_rc";
|
}
|
}
|
|
if($flag_str =~ /#clr_acy/){
|
|
$uinst->{flags} = $uinst->{flags}." #clr_acy";
|
|
}
|
|
|
if($error ne ''){
|
if($error ne ''){
|
$num_errors++;
|
$num_errors++;
|
$uinst->{error} = $error;
|
$uinst->{error} = $error;
|
};
|
};
|
