| Line 59... |
Line 59... |
// interrupt enable register
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// interrupt enable register
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input [3:0] intr_ena; // set high to enable respective interrupt
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input [3:0] intr_ena; // set high to enable respective interrupt
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// 8080 assembly code constants
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// 8080 assembly code constants
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// call instruction opcode used to call interrupt routine
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// RST instruction opcode used to call interrupt routines at addresses
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`define CALL_INST 8'hcd
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// int0: 0x08 / int1: 0x18 / int2: 0x28 / int3: 0x38
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// interrupt vectors fixed addresses - high address byte is 0
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`define RST_1_INST 8'hcf
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`define INT0_VEC 8'h08
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`define RST_3_INST 8'hdf
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`define INT1_VEC 8'h18
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`define RST_5_INST 8'hef
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`define INT2_VEC 8'h28
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`define RST_7_INST 8'hff
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`define INT3_VEC 8'h38
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// internal declarations
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// internal declarations
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// registered output
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// registered output
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reg [7:0] cpu_inst;
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reg [7:0] cpu_inst;
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| Line 103... |
Line 102... |
else if (act_int[3]) intSel <= 2'd2;
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else if (act_int[3]) intSel <= 2'd2;
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else intSel <= 2'd3;
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else intSel <= 2'd3;
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// switch to next state
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// switch to next state
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intSq <= 2'd1;
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intSq <= 2'd1;
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end
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end
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default: // all other states increment the state register on inta read
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2'd1: // wait for inta read cycle
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if (cpu_inta && cpu_rd)
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if (cpu_inta && cpu_rd)
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begin
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begin
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// update state
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// update instruction opcode
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intSq <= intSq + 1;
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cpu_inst <= int_vec;
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// switch to end for inta release
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// update instruction opcode for each byte read during inta
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intSq <= 2'd2;
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case (intSq)
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2'd1: cpu_inst <= `CALL_INST;
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2'd2: cpu_inst <= int_vec;
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default: cpu_inst <= 8'd0;
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endcase
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end
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end
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else if (!cpu_inta)
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default: // wait for inta end
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if (!cpu_inta)
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begin
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begin
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intSq <= 2'd0;
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// reset state machine
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cpu_inst <= 8'd0;
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intSq <= 2'b0;
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cpu_inst <= 8'b0;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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// assign interrupt vector address according to selected interrupt
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// assign interrupt vector address according to selected interrupt
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always @ (intSel)
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always @ (intSel)
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begin
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begin
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case (intSel)
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case (intSel)
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2'd0: int_vec <= `INT0_VEC;
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2'd0: int_vec <= `RST_1_INST;
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2'd1: int_vec <= `INT1_VEC;
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2'd1: int_vec <= `RST_3_INST;
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2'd2: int_vec <= `INT2_VEC;
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2'd2: int_vec <= `RST_5_INST;
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2'd3: int_vec <= `INT3_VEC;
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2'd3: int_vec <= `RST_7_INST;
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endcase
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endcase
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end
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end
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// latch active interrupt on rising edge
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// latch active interrupt on rising edge
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always @ (posedge reset or posedge clock)
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always @ (posedge reset or posedge clock)
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| Line 150... |
Line 146... |
assign cpu_intr = |act_int;
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assign cpu_intr = |act_int;
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// clear serviced interrupt
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// clear serviced interrupt
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always @ (cpu_inta or cpu_rd or intSq or intSel)
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always @ (cpu_inta or cpu_rd or intSq or intSel)
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begin
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begin
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if (cpu_inta && cpu_rd && (intSq == 2'd3))
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if (cpu_inta && cpu_rd && (intSq == 2'd1))
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begin
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begin
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case (intSel)
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case (intSel)
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2'd0: int_clr <= 4'b0001;
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2'd0: int_clr <= 4'b0001;
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2'd1: int_clr <= 4'b0010;
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2'd1: int_clr <= 4'b0010;
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2'd2: int_clr <= 4'b0100;
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2'd2: int_clr <= 4'b0100;
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